diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-03-19 10:11:57 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2014-03-19 10:11:57 +0000 |
| commit | c322035d6b195ef2032c25253fdda5bd831bee7c (patch) | |
| tree | 5c0523f731f34d86c1daaa830e300d218bfec38c /os/hal | |
| parent | b54cc0d618dbf54b384ad88897489c45c94e6692 (diff) | |
| download | ChibiOS-c322035d6b195ef2032c25253fdda5bd831bee7c.tar.gz ChibiOS-c322035d6b195ef2032c25253fdda5bd831bee7c.tar.bz2 ChibiOS-c322035d6b195ef2032c25253fdda5bd831bee7c.zip | |
Fixed bug #476.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6789 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/ports/STM32/STM32L1xx/hal_lld.h | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/os/hal/ports/STM32/STM32L1xx/hal_lld.h b/os/hal/ports/STM32/STM32L1xx/hal_lld.h index ff1ec009f..2953afc19 100644 --- a/os/hal/ports/STM32/STM32L1xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L1xx/hal_lld.h @@ -340,7 +340,7 @@ /**
* @brief HSE divider toward RTC setting.
*/
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#if !defined(STM32_RTCPRE) || defined(__DOXYGEN__)
#define STM32_RTCPRE STM32_RTCPRE_DIV2
#endif
/** @} */
@@ -459,7 +459,7 @@ (STM32_MCOSEL == STM32_MCOSEL_HSE) || \
((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
- (STM_RTC_SOURCE == STM32_RTCSEL_HSEDIV)
+ (STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
#error "required HSE clock is not enabled"
#endif
#endif /* !STM32_HSE_ENABLED */
@@ -467,7 +467,7 @@ /* LSI related checks.*/
#if STM32_LSI_ENABLED
#else /* !STM32_LSI_ENABLED */
-#if STM_RTCCLK == STM32_LSICLK
+#if STM32_RTCCLK == STM32_LSICLK
#error "required LSI clock is not enabled"
#endif
#endif /* !STM32_LSI_ENABLED */
@@ -481,7 +481,7 @@ #error "STM32_LSECLK outside acceptable range (1...1000kHz)"
#endif
#else /* !STM32_LSE_ENABLED */
-#if STM_RTCCLK == STM32_LSECLK
+#if STM32_RTCCLK == STM32_LSECLK
#error "required LSE clock is not enabled"
#endif
#endif /* !STM32_LSE_ENABLED */
@@ -695,19 +695,19 @@ * @brief MCO divider clock.
*/
#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM_MCODIVCLK 0
+#define STM32_MCODIVCLK 0
#elif STM32_MCOSEL == STM32_MCOSEL_HSI
-#define STM_MCODIVCLK STM32_HSICLK
+#define STM32_MCODIVCLK STM32_HSICLK
#elif STM32_MCOSEL == STM32_MCOSEL_MSI
-#define STM_MCODIVCLK STM32_MSICLK
+#define STM32_MCODIVCLK STM32_MSICLK
#elif STM32_MCOSEL == STM32_MCOSEL_HSE
-#define STM_MCODIVCLK STM32_HSECLK
+#define STM32_MCODIVCLK STM32_HSECLK
#elif STM32_MCOSEL == STM32_MCOSEL_PLL
-#define STM_MCODIVCLK STM32_PLLCLKOUT
+#define STM32_MCODIVCLK STM32_PLLCLKOUT
#elif STM32_MCOSEL == STM32_MCOSEL_LSI
-#define STM_MCODIVCLK STM32_LSICLK
+#define STM32_MCODIVCLK STM32_LSICLK
#elif STM32_MCOSEL == STM32_MCOSEL_LSE
-#define STM_MCODIVCLK STM32_LSECLK
+#define STM32_MCODIVCLK STM32_LSECLK
#else
#error "invalid STM32_MCOSEL value specified"
#endif
@@ -716,15 +716,15 @@ * @brief MCO output pin clock.
*/
#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
-#define STM_MCOCLK STM_MCODIVCLK
+#define STM32_MCOCLK STM32_MCODIVCLK
#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
-#define STM_MCOCLK (STM_MCODIVCLK / 2)
+#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
-#define STM_MCOCLK (STM_MCODIVCLK / 4)
+#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
-#define STM_MCOCLK (STM_MCODIVCLK / 8)
+#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
-#define STM_MCOCLK (STM_MCODIVCLK / 16)
+#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
#else
#error "invalid STM32_MCOPRE value specified"
#endif
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