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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-07-22 09:29:16 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-07-22 09:29:16 +0000 |
| commit | bece446faacd59c9a48c391cb34fac76fdbabac6 (patch) | |
| tree | 8225456ae17b03f4b7c56358e157201d8ec05d7f /os/hal | |
| parent | 17f1a787340533d5cd20b052355b6bbcb38ed1ba (diff) | |
| download | ChibiOS-bece446faacd59c9a48c391cb34fac76fdbabac6.tar.gz ChibiOS-bece446faacd59c9a48c391cb34fac76fdbabac6.tar.bz2 ChibiOS-bece446faacd59c9a48c391cb34fac76fdbabac6.zip | |
Fixed bug #967.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12186 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.h | 34 |
1 files changed, 31 insertions, 3 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h index c2a861b4c..d18ed02e2 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -488,7 +488,7 @@ #endif
/**
- * @brief STM32_PLLPDIV_VALUE divider value or zero if disabled.
+ * @brief PLLPDIV divider value or zero if disabled.
* @note The allowed values are 0, 2..31.
*/
#if !defined(STM32_PLLPDIV_VALUE) || defined(__DOXYGEN__)
@@ -585,6 +585,14 @@ #endif
/**
+ * @brief PLLSAI1PDIV divider value or zero if disabled.
+ * @note The allowed values are 0, 2..31.
+ */
+#if !defined(STM32_PLLSAI1PDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI1PDIV_VALUE 0
+#endif
+
+/**
* @brief PLLSAI1P divider value.
* @note The allowed values are 7, 17.
*/
@@ -617,6 +625,14 @@ #endif
/**
+ * @brief PLLSAI2PDIV divider value or zero if disabled.
+ * @note The allowed values are 0, 2..31.
+ */
+#if !defined(STM32_PLLSAI2PDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLSAI2PDIV_VALUE 0
+#endif
+
+/**
* @brief PLLSAI2P divider value.
* @note The allowed values are 7, 17.
*/
@@ -914,9 +930,9 @@ #elif STM32_VOS == STM32_VOS_RANGE2
#define STM32_SYSCLK_MAX 26000000
-#define STM32_HSECLK_MAX 48000000
+#define STM32_HSECLK_MAX 26000000
#define STM32_HSECLK_BYP_MAX 26000000
-#define STM32_HSECLK_MIN 4000000
+#define STM32_HSECLK_MIN 8000000
#define STM32_HSECLK_BYP_MIN 8000000
#define STM32_LSECLK_MAX 32768
#define STM32_LSECLK_BYP_MAX 1000000
@@ -1331,7 +1347,11 @@ /**
* @brief PLL P output clock frequency.
*/
+#if (STM32_PLLPDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE)
+#else
+#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLPDIV_VALUE)
+#endif
/**
* @brief PLL Q output clock frequency.
@@ -1632,7 +1652,11 @@ /**
* @brief PLLSAI1-P output clock frequency.
*/
+#if (STM32_PLLSAI1PDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1P_VALUE)
+#else
+#define STM32_PLLSAI1_P_CLKOUT (STM32_PLLSAI1VCO / STM32_PLLSAI1PDIV_VALUE)
+#endif
/**
* @brief PLLSAI1-Q output clock frequency.
@@ -1778,7 +1802,11 @@ /**
* @brief PLLSAI2-P output clock frequency.
*/
+#if (STM32_PLLSAI2PDIV_VALUE == 0) || defined(__DOXYGEN__)
#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2P_VALUE)
+#else
+#define STM32_PLLSAI2_P_CLKOUT (STM32_PLLSAI2VCO / STM32_PLLSAI2PDIV_VALUE)
+#endif
/**
* @brief PLLSAI2-R output clock frequency.
|