Mass update for TIM-related changes.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12526 110e8d01-0319-4d1e-a829-52ad28d1bb01

6 files changed, 554 insertions, 15 deletions

diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_isr.c b/os/hal/ports/STM32/STM32F3xx/stm32_isr.c
index e91ce2508..a46ca0f9c 100644
--- a/os/hal/ports/STM32/STM32F3xx/stm32_isr.c
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_isr.c
@@ -325,7 +325,7 @@ OSAL_IRQ_HANDLER(VectorAC) {
 

   OSAL_IRQ_EPILOGUE();

 }

-#endif /* HAL_USE_GPT */

+#endif /* HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM */

 

 /*===========================================================================*/

 /* Driver exported functions.                                                */

diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
index 03d87e5e0..38968038e 100644
--- a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
@@ -297,6 +297,83 @@
 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

+/* IRQ priority checks.*/

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI1_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI1_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI3_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI3_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI5_9_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI5_9_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI10_15_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI10_15_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI16_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI16_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI17_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI17_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI18_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI18_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI19_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI19_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI20_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI20_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI21_22_29_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_22_29_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI30_32_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI30_32_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI33_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI33_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM15_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_TIM16_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM16_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_isr.c b/os/hal/ports/STM32/STM32L4xx+/stm32_isr.c
index d087d8374..228152904 100644
--- a/os/hal/ports/STM32/STM32L4xx+/stm32_isr.c
+++ b/os/hal/ports/STM32/STM32L4xx+/stm32_isr.c
@@ -212,6 +212,122 @@ OSAL_IRQ_HANDLER(VectorE0) {
 

 #endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */

 

+#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)

+/**

+ * @brief   TIM1-BRK, TIM15 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorA0) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+#if STM32_GPT_USE_TIM15

+  gpt_lld_serve_interrupt(&GPTD15);

+#endif

+#endif

+#if HAL_USE_ICU

+#if STM32_ICU_USE_TIM15

+  icu_lld_serve_interrupt(&ICUD15);

+#endif

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM15

+  pwm_lld_serve_interrupt(&PWMD15);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   TIM1-UP, TIM16 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorA4) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+#if STM32_GPT_USE_TIM1

+  gpt_lld_serve_interrupt(&GPTD1);

+#endif

+#if STM32_GPT_USE_TIM16

+  gpt_lld_serve_interrupt(&GPTD16);

+#endif

+#endif

+#if HAL_USE_ICU

+#if STM32_ICU_USE_TIM1

+  icu_lld_serve_interrupt(&ICUD1);

+#endif

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM1

+  pwm_lld_serve_interrupt(&PWMD1);

+#endif

+#if STM32_PWM_USE_TIM16

+  pwm_lld_serve_interrupt(&PWMD16);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   TIM1-TRG-COM, TIM17 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorA8) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+#if STM32_GPT_USE_TIM17

+  gpt_lld_serve_interrupt(&GPTD17);

+#endif

+#endif

+#if HAL_USE_ICU

+  /* Not used by ICU.*/

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM17

+  pwm_lld_serve_interrupt(&PWMD17);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   TIM1-CC interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorAC) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+  /* Not used by GPT.*/

+#endif

+#if HAL_USE_ICU

+#if STM32_ICU_USE_TIM1

+  icu_lld_serve_interrupt(&ICUD1);

+#endif

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM1

+  pwm_lld_serve_interrupt(&PWMD1);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+#endif /* HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM */

+

 /*===========================================================================*/

 /* Driver exported functions.                                                */

 /*===========================================================================*/

@@ -224,13 +340,19 @@ OSAL_IRQ_HANDLER(VectorE0) {
 void irqInit(void) {

 

 #if HAL_USE_PAL

-  nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);

-  nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);

-  nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY);

-  nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);

-  nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);

-  nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);

-  nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);

+  nvicEnableVector(EXTI0_IRQn,              STM32_IRQ_EXTI0_PRIORITY);

+  nvicEnableVector(EXTI1_IRQn,              STM32_IRQ_EXTI1_PRIORITY);

+  nvicEnableVector(EXTI2_IRQn,              STM32_IRQ_EXTI2_PRIORITY);

+  nvicEnableVector(EXTI3_IRQn,              STM32_IRQ_EXTI3_PRIORITY);

+  nvicEnableVector(EXTI4_IRQn,              STM32_IRQ_EXTI4_PRIORITY);

+  nvicEnableVector(EXTI9_5_IRQn,            STM32_IRQ_EXTI5_9_PRIORITY);

+  nvicEnableVector(EXTI15_10_IRQn,          STM32_IRQ_EXTI10_15_PRIORITY);

+#endif

+#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)

+  nvicEnableVector(TIM1_BRK_TIM15_IRQn,     STM32_IRQ_TIM1_BRK_TIM15_PRIORITY);

+  nvicEnableVector(TIM1_UP_TIM16_IRQn,      STM32_IRQ_TIM1_UP_TIM16_PRIORITY);

+  nvicEnableVector(TIM1_TRG_COM_TIM17_IRQn, STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY);

+  nvicEnableVector(TIM1_CC_IRQn,            STM32_IRQ_TIM1_CC_PRIORITY);

 #endif

 }

 

@@ -250,6 +372,12 @@ void irqDeinit(void) {
   nvicDisableVector(EXTI9_5_IRQn);

   nvicDisableVector(EXTI15_10_IRQn);

 #endif

+#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)

+  nvicDisableVector(TIM1_BRK_TIM15_IRQn);

+  nvicDisableVector(TIM1_UP_TIM16_IRQn);

+  nvicDisableVector(TIM1_TRG_COM_TIM17_IRQn);

+  nvicDisableVector(TIM1_CC_IRQn);

+#endif

 }

 

 /** @} */

diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h b/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h
index 85c9f6fe4..b4c1b7b35 100644
--- a/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32L4xx+/stm32_isr.h
@@ -29,6 +29,16 @@
 /* Driver constants.                                                         */

 /*===========================================================================*/

 

+/**

+ * @name    ISRs suppressed in standard drivers

+ * @{

+ */

+#define STM32_TIM1_SUPPRESS_ISR

+#define STM32_TIM15_SUPPRESS_ISR

+#define STM32_TIM16_SUPPRESS_ISR

+#define STM32_TIM17_SUPPRESS_ISR

+/** @} */

+

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -120,12 +130,105 @@
 #if !defined(STM32_IRQ_EXTI21_22_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_IRQ_EXTI21_22_PRIORITY        6

 #endif

+

+/**

+ * @brief   TIM1-BRK, TIM15 interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY   7

+#endif

+

+/**

+ * @brief   TIM1-UP, TIM16 interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_UP_TIM16_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY    7

+#endif

+

+/**

+ * @brief   TIM1-TRG-COM, TIM17 interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7

+#endif

+

+/**

+ * @brief   TIM1-CC interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_CC_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_CC_PRIORITY          7

+#endif

 /** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

+/* IRQ priority checks.*/

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI1_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI1_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI3_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI3_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI5_9_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI5_9_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI10_15_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI10_15_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI1635_38_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI1635_38_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI18_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI18_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI19_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI19_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI20_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI20_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI21_22_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_22_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM15_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_TIM16_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM16_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/

diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_isr.c b/os/hal/ports/STM32/STM32L4xx/stm32_isr.c
index e556586dc..17c463c27 100644
--- a/os/hal/ports/STM32/STM32L4xx/stm32_isr.c
+++ b/os/hal/ports/STM32/STM32L4xx/stm32_isr.c
@@ -212,6 +212,122 @@ OSAL_IRQ_HANDLER(VectorE0) {
 

 #endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */

 

+#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)

+/**

+ * @brief   TIM1-BRK, TIM15 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorA0) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+#if STM32_GPT_USE_TIM15

+  gpt_lld_serve_interrupt(&GPTD15);

+#endif

+#endif

+#if HAL_USE_ICU

+#if STM32_ICU_USE_TIM15

+  icu_lld_serve_interrupt(&ICUD15);

+#endif

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM15

+  pwm_lld_serve_interrupt(&PWMD15);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   TIM1-UP, TIM16 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorA4) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+#if STM32_GPT_USE_TIM1

+  gpt_lld_serve_interrupt(&GPTD1);

+#endif

+#if STM32_GPT_USE_TIM16

+  gpt_lld_serve_interrupt(&GPTD16);

+#endif

+#endif

+#if HAL_USE_ICU

+#if STM32_ICU_USE_TIM1

+  icu_lld_serve_interrupt(&ICUD1);

+#endif

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM1

+  pwm_lld_serve_interrupt(&PWMD1);

+#endif

+#if STM32_PWM_USE_TIM16

+  pwm_lld_serve_interrupt(&PWMD16);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   TIM1-TRG-COM, TIM17 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorA8) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+#if STM32_GPT_USE_TIM17

+  gpt_lld_serve_interrupt(&GPTD17);

+#endif

+#endif

+#if HAL_USE_ICU

+  /* Not used by ICU.*/

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM17

+  pwm_lld_serve_interrupt(&PWMD17);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   TIM1-CC interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorAC) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+  /* Not used by GPT.*/

+#endif

+#if HAL_USE_ICU

+#if STM32_ICU_USE_TIM1

+  icu_lld_serve_interrupt(&ICUD1);

+#endif

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM1

+  pwm_lld_serve_interrupt(&PWMD1);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+#endif /* HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM */

+

 /*===========================================================================*/

 /* Driver exported functions.                                                */

 /*===========================================================================*/

@@ -224,13 +340,19 @@ OSAL_IRQ_HANDLER(VectorE0) {
 void irqInit(void) {

 

 #if HAL_USE_PAL

-  nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);

-  nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);

-  nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY);

-  nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);

-  nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);

-  nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);

-  nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);

+  nvicEnableVector(EXTI0_IRQn,              STM32_IRQ_EXTI0_PRIORITY);

+  nvicEnableVector(EXTI1_IRQn,              STM32_IRQ_EXTI1_PRIORITY);

+  nvicEnableVector(EXTI2_IRQn,              STM32_IRQ_EXTI2_PRIORITY);

+  nvicEnableVector(EXTI3_IRQn,              STM32_IRQ_EXTI3_PRIORITY);

+  nvicEnableVector(EXTI4_IRQn,              STM32_IRQ_EXTI4_PRIORITY);

+  nvicEnableVector(EXTI9_5_IRQn,            STM32_IRQ_EXTI5_9_PRIORITY);

+  nvicEnableVector(EXTI15_10_IRQn,          STM32_IRQ_EXTI10_15_PRIORITY);

+#endif

+#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)

+  nvicEnableVector(TIM1_BRK_TIM15_IRQn,     STM32_IRQ_TIM1_BRK_TIM15_PRIORITY);

+  nvicEnableVector(TIM1_UP_TIM16_IRQn,      STM32_IRQ_TIM1_UP_TIM16_PRIORITY);

+  nvicEnableVector(TIM1_TRG_COM_TIM17_IRQn, STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY);

+  nvicEnableVector(TIM1_CC_IRQn,            STM32_IRQ_TIM1_CC_PRIORITY);

 #endif

 }

 

@@ -250,6 +372,12 @@ void irqDeinit(void) {
   nvicDisableVector(EXTI9_5_IRQn);

   nvicDisableVector(EXTI15_10_IRQn);

 #endif

+#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)

+  nvicDisableVector(TIM1_BRK_TIM15_IRQn);

+  nvicDisableVector(TIM1_UP_TIM16_IRQn);

+  nvicDisableVector(TIM1_TRG_COM_TIM17_IRQn);

+  nvicDisableVector(TIM1_CC_IRQn);

+#endif

 }

 

 /** @} */

diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_isr.h b/os/hal/ports/STM32/STM32L4xx/stm32_isr.h
index ab33b2584..9ca8e2594 100644
--- a/os/hal/ports/STM32/STM32L4xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32L4xx/stm32_isr.h
@@ -29,6 +29,16 @@
 /* Driver constants.                                                         */

 /*===========================================================================*/

 

+/**

+ * @name    ISRs suppressed in standard drivers

+ * @{

+ */

+#define STM32_TIM1_SUPPRESS_ISR

+#define STM32_TIM15_SUPPRESS_ISR

+#define STM32_TIM16_SUPPRESS_ISR

+#define STM32_TIM17_SUPPRESS_ISR

+/** @} */

+

 /*===========================================================================*/

 /* Driver pre-compile time settings.                                         */

 /*===========================================================================*/

@@ -120,12 +130,105 @@
 #if !defined(STM32_IRQ_EXTI21_22_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_IRQ_EXTI21_22_PRIORITY        6

 #endif

+

+/**

+ * @brief   TIM1-BRK, TIM15 interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY   7

+#endif

+

+/**

+ * @brief   TIM1-UP, TIM16 interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_UP_TIM16_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY    7

+#endif

+

+/**

+ * @brief   TIM1-TRG-COM, TIM17 interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7

+#endif

+

+/**

+ * @brief   TIM1-CC interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_CC_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_CC_PRIORITY          7

+#endif

 /** @} */

 

 /*===========================================================================*/

 /* Derived constants and error checks.                                       */

 /*===========================================================================*/

 

+/* IRQ priority checks.*/

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI0_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI0_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI1_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI1_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI2_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI2_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI3_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI3_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI4_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI4_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI5_9_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI5_9_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI10_15_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI10_15_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI1635_38_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI1635_38_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI18_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI18_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI19_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI19_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI20_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI20_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_EXTI21_22_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_EXTI21_22_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_BRK_TIM15_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_UP_TIM16_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_UP_TIM16_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY"

+#endif

+

+#if !OSAL_IRQ_IS_VALID_PRIORITY(STM32_IRQ_TIM1_CC_PRIORITY)

+#error "Invalid IRQ priority assigned to STM32_IRQ_TIM1_CC_PRIORITY"

+#endif

+

 /*===========================================================================*/

 /* Driver data structures and types.                                         */

 /*===========================================================================*/