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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-01-14 12:23:42 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-01-14 12:23:42 +0000
commita41f12ad8a925c8baaaeb826e63589721f942f4a (patch)
tree7e0fbfe52976723e152aeb106fd88f8c873e517a /os/hal
parent685286c5c8a6ad0d9370e62ea51eb6492e359d2a (diff)
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RTC. Added possibility of changing RTC clock source.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3809 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
-rw-r--r--os/hal/platforms/STM32/RTCv1/rtc_lld.c4
-rw-r--r--os/hal/platforms/STM32F1xx/hal_lld.c27
-rw-r--r--os/hal/platforms/STM32F1xx/hal_lld_f100.h1
-rw-r--r--os/hal/platforms/STM32F1xx/hal_lld_f103.h1
-rw-r--r--os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h1
5 files changed, 22 insertions, 12 deletions
diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
index 811920e06..4344f17bb 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c
+++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
@@ -101,6 +101,10 @@ CH_IRQ_HANDLER(RTC_IRQHandler) {
CH_IRQ_PROLOGUE();
+ /* This wait works only when AHB1 bus was previously powered off by any
+ reason (standby, reset, etc). In other cases it does nothing.*/
+ rtc_lld_apb1_sync();
+
/* Mask of all enabled and pending sources.*/
flags = RTC->CRH & RTC->CRL;
RTC->CRL &= ~(RTC_CRL_SECF | RTC_CRL_ALRF | RTC_CRL_OWF);
diff --git a/os/hal/platforms/STM32F1xx/hal_lld.c b/os/hal/platforms/STM32F1xx/hal_lld.c
index f903106cb..75afa0a84 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld.c
+++ b/os/hal/platforms/STM32F1xx/hal_lld.c
@@ -43,22 +43,25 @@
/**
* @brief Initializes the backup domain.
+ * @note WARNING! Changing clock source impossible without resetting
+ * of the whole BKP domain.
*/
static void hal_lld_backup_domain_init(void) {
/* Backup domain access enabled and left open.*/
- PWR->CR = PWR_CR_DBP;
+ PWR->CR |= PWR_CR_DBP;
- /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
- if ((RCC->BDCR & RCC_BDCR_LSEON) == 0) {
- /* Backup domain reset.*/
+ /* Reset BKP domain if different clock source selected.*/
+ if ((RCC->BDCR & STM32_RTCSEL_MSK) != STM32_RTCSEL){
RCC->BDCR = RCC_BDCR_BDRST;
RCC->BDCR = 0;
- RCC->BDCR = RCC_BDCR_LSEON;
- while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
- ; /* Waits until LSE is stable. */
}
+
+ /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+ RCC->BDCR |= RCC_BDCR_LSEON;
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Waits until LSE is stable. */
#endif
#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
@@ -66,7 +69,7 @@ static void hal_lld_backup_domain_init(void) {
initialization.*/
if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
/* Selects clock source.*/
- RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTCSEL;
+ RCC->BDCR |= STM32_RTCSEL;
/* RTC clock enabled.*/
RCC->BDCR |= RCC_BDCR_RTCEN;
@@ -213,7 +216,7 @@ void stm32_clock_init(void) {
/* HSE activation.*/
RCC->CR |= RCC_CR_HSEON;
while (!(RCC->CR & RCC_CR_HSERDY))
- ; /* Waits until HSE is stable. */
+ ; /* Waits until HSE is stable. */
#endif
#if STM32_LSI_ENABLED
@@ -231,14 +234,14 @@ void stm32_clock_init(void) {
#if STM32_ACTIVATE_PLL2
RCC->CR |= RCC_CR_PLL2ON;
while (!(RCC->CR & RCC_CR_PLL2RDY))
- ; /* Waits until PLL2 is stable. */
+ ; /* Waits until PLL2 is stable. */
#endif
/* PLL3 setup, if activated.*/
#if STM32_ACTIVATE_PLL3
RCC->CR |= RCC_CR_PLL3ON;
while (!(RCC->CR & RCC_CR_PLL3RDY))
- ; /* Waits until PLL3 is stable. */
+ ; /* Waits until PLL3 is stable. */
#endif
/* PLL1 setup, if activated.*/
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f100.h b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
index 766e9e48a..c30f2a7dc 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f100.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f100.h
@@ -174,6 +174,7 @@
#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
RTC clock. */
+#define STM32_RTCSEL_MSK (3 << 8) /**< RTC clock source mask. */
/** @} */
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f103.h b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
index 39b13cf38..b8aa67374 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f103.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f103.h
@@ -184,6 +184,7 @@
#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
RTC clock. */
+#define STM32_RTCSEL_MSK (3 << 8) /**< RTC clock source mask. */
/** @} */
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
index 8e63ebaf3..53bebc3b2 100644
--- a/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
+++ b/os/hal/platforms/STM32F1xx/hal_lld_f105_f107.h
@@ -194,6 +194,7 @@
#define STM32_RTCSEL_LSI (2 << 8) /**< LSI used as RTC clock. */
#define STM32_RTCSEL_HSEDIV (3 << 8) /**< HSE divided by 128 used as
RTC clock. */
+#define STM32_RTCSEL_MSK (3 << 8) /**< RTC clock source mask. */
/** @} */
/**