diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-03-13 08:27:25 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-03-13 08:27:25 +0000 |
| commit | a1427e9a2201f3b87eace5b11ad64992197dfdf1 (patch) | |
| tree | fa278295129d6852f3c9f611a1891cbd93870e3c /os/hal | |
| parent | 887409c0c96c911862f21955ee956e5fa2d8ad6f (diff) | |
| download | ChibiOS-a1427e9a2201f3b87eace5b11ad64992197dfdf1.tar.gz ChibiOS-a1427e9a2201f3b87eace5b11ad64992197dfdf1.tar.bz2 ChibiOS-a1427e9a2201f3b87eace5b11ad64992197dfdf1.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2821 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld_f105_f107.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/os/hal/platforms/STM32/hal_lld_f105_f107.h b/os/hal/platforms/STM32/hal_lld_f105_f107.h index fd4f96aa0..b28f8c297 100644 --- a/os/hal/platforms/STM32/hal_lld_f105_f107.h +++ b/os/hal/platforms/STM32/hal_lld_f105_f107.h @@ -324,7 +324,6 @@ #if STM32_ACTIVATE_PLL2 && \
(STM32_PREDIV1SRC != STM32_PREDIV1SRC_PLL2) && \
(STM32_MCO != STM32_MCO_PLL2)
-
#error "PLL2 activated but not used"
#endif
@@ -442,10 +441,15 @@ #endif
#endif /* STM32_ACTIVATE_PLL3 */
+/* The following values are only used if PLL1 is activated */
+#if STM32_ACTIVATE_PLL1
/**
* @brief PREDIV1 input frequency.
*/
#if (STM32_PREDIV1SRC == STM32_PREDIV1SRC_PLL2) || defined(__DOXYGEN__)
+#if !STM32_ACTIVATE_PLL2
+#error "PLL2 selected as clock source for STM32_PREDIV1SRC but not activated"
+#endif
#define STM32_PREDIV1CLK STM32_PLL2CLKOUT
#elif STM32_PREDIV1SRC == STM32_PREDIV1SRC_HSE
#define STM32_PREDIV1CLK STM32_HSECLK
@@ -483,11 +487,15 @@ #if (STM32_PLLVCO < 36000000) || (STM32_PLLVCO > 144000000)
#error "STM32_PLLVCO outside acceptable range (36...144MHz)"
#endif
+#endif /* STM32_ACTIVATE_PLL1 */
/**
* @brief System clock source.
*/
#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#if !STM32_ACTIVATE_PLL1
+#error "PLL1 selected as clock source for STM32_SYSCLK but not activated"
+#endif
#define STM32_SYSCLK STM32_PLLCLKOUT
#elif (STM32_SW == STM32_SW_HSI)
#define STM32_SYSCLK STM32_HSICLK
|