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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-12-25 11:30:44 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-12-25 11:30:44 +0000 |
| commit | 99cee8a6ed66b380c8d29fa82413dcc659b6068a (patch) | |
| tree | 3ee8a44cfbcc9033bd6407c814456c68b104188c /os/hal | |
| parent | 582b0dbf53613ad0045159b113fce6d84c4cbf4f (diff) | |
| download | ChibiOS-99cee8a6ed66b380c8d29fa82413dcc659b6068a.tar.gz ChibiOS-99cee8a6ed66b380c8d29fa82413dcc659b6068a.tar.bz2 ChibiOS-99cee8a6ed66b380c8d29fa82413dcc659b6068a.zip | |
Added USB clock configuration to the STM32 HAL driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@2531 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld.c | 5 | ||||
| -rw-r--r-- | os/hal/platforms/STM32/hal_lld_f103.h | 21 |
2 files changed, 24 insertions, 2 deletions
diff --git a/os/hal/platforms/STM32/hal_lld.c b/os/hal/platforms/STM32/hal_lld.c index faa265f59..b83262722 100644 --- a/os/hal/platforms/STM32/hal_lld.c +++ b/os/hal/platforms/STM32/hal_lld.c @@ -113,8 +113,9 @@ void stm32_clock_init(void) { #endif
/* Clock settings.*/
- RCC->CFGR = STM32_MCO | STM32_PLLMUL | STM32_PLLXTPRE | STM32_PLLSRC |
- STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;
+ RCC->CFGR = STM32_MCO | STM32_USBPRE | STM32_PLLMUL | STM32_PLLXTPRE |
+ STM32_PLLSRC | STM32_ADCPRE | STM32_PPRE2 | STM32_PPRE1 |
+ STM32_HPRE;
/* Flash setup and final clock selection. */
FLASH->ACR = STM32_FLASHBITS; /* Flash wait states depending on clock. */
diff --git a/os/hal/platforms/STM32/hal_lld_f103.h b/os/hal/platforms/STM32/hal_lld_f103.h index 8e5b25053..5adec93dc 100644 --- a/os/hal/platforms/STM32/hal_lld_f103.h +++ b/os/hal/platforms/STM32/hal_lld_f103.h @@ -80,6 +80,9 @@ #define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
+#define STM32_USBPRE_DIV1P5 (0 << 22) /**< PLLOUT divided by 1.5. */
+#define STM32_USBPRE_DIV1 (1 << 22) /**< PLLOUT divided by 1. */
+
#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */
@@ -244,6 +247,13 @@ #endif
/**
+ * @brief USB prescaler initialization.
+ */
+#if !defined(STM32_USEUSB) || defined(__DOXYGEN__)
+#define STM32_USBPRE STM32_USBPRE_DIV1P5
+#endif
+
+/**
* @brief MCO pin setting.
*/
#if !defined(STM32_MCO) || defined(__DOXYGEN__)
@@ -406,6 +416,17 @@ #error "invalid STM32_ADCPRE value specified"
#endif
+/**
+ * @brief USB frequency.
+ */
+#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
+#define STM32_USBCLK ((STM32_PLLCLKOUT * 2) / 3)
+#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
+#define STM32_USBCLK STM32_PLLCLKOUT
+#else
+#error "invalid STM32_USBPRE value specified"
+#endif
+
/* ADC frequency check.*/
#if STM32_ADCCLK > 14000000
#error "STM32_ADCCLK exceeding maximum frequency (14MHz)"
|