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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-30 10:18:03 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-10-30 10:18:03 +0000 |
| commit | 7bf28b012a094534d25ba52d710ef7fa9d3f8767 (patch) | |
| tree | 7940cdaf431da8e5afeadc54ff2f50fa80b104a0 /os/hal | |
| parent | 31df47b920a3d66bff8645ed20b4fe8480929a39 (diff) | |
| download | ChibiOS-7bf28b012a094534d25ba52d710ef7fa9d3f8767.tar.gz ChibiOS-7bf28b012a094534d25ba52d710ef7fa9d3f8767.tar.bz2 ChibiOS-7bf28b012a094534d25ba52d710ef7fa9d3f8767.zip | |
Fixed bug #658.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8412 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.c | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/hal_lld.h | 79 |
2 files changed, 81 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c index 87fc9af15..325991e13 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c @@ -307,8 +307,8 @@ void stm32_clock_init(void) { #endif
/* Clock settings.*/
- RCC->CFGR = STM32_MCOSEL | STM32_PLLMUL | STM32_PLLSRC |
- STM32_PPRE | STM32_HPRE;
+ RCC->CFGR = STM32_PLLNODIV | STM32_MCOPRE | STM32_MCOSEL | STM32_PLLMUL |
+ STM32_PLLSRC | STM32_PPRE | STM32_HPRE;
RCC->CFGR2 = STM32_PREDIV;
#if STM32_CECSW == STM32_CECSW_OFF
RCC->CFGR3 = STM32_USBSW | STM32_I2C1SW | STM32_USART1SW;
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.h b/os/hal/ports/STM32/STM32F0xx/hal_lld.h index cb2c4129f..68706ee1a 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.h @@ -229,6 +229,19 @@ #define STM32_MCOSEL_HSE (6 << 24) /**< HSE clock on MCO pin. */
#define STM32_MCOSEL_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
#define STM32_MCOSEL_HSI48 (8 << 24) /**< HSI48 clock on MCO pin. */
+
+#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
+#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 2. */
+#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 4. */
+#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 8. */
+#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 16. */
+#define STM32_MCOPRE_DIV32 (5 << 28) /**< MCO divided by 32. */
+#define STM32_MCOPRE_DIV64 (6 << 28) /**< MCO divided by 64. */
+#define STM32_MCOPRE_DIV128 (7 << 28) /**< MCO divided by 128. */
+
+#define STM32_PLLNODIV_MASK (1 << 31) /**< MCO PLL divider mask. */
+#define STM32_PLLNODIV_DIV2 (0 << 31) /**< MCO PLL is divided by two. */
+#define STM32_PLLNODIV_DIV1 (1 << 31) /**< MCO PLL is divided by one. */
/** @} */
/**
@@ -405,6 +418,20 @@ #endif
/**
+ * @brief MCO divider setting.
+ */
+#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#endif
+
+/**
+ * @brief MCO PLL divider setting.
+ */
+#if !defined(STM32_PLLNODIV) || defined(__DOXYGEN__)
+#define STM32_PLLNODIV STM32_PLLNODIV_DIV2
+#endif
+
+/**
* @brief USB Clock source.
*/
#if !defined(STM32_USBSW) || defined(__DOXYGEN__)
@@ -741,6 +768,58 @@ #error "STM32_PCLK exceeding maximum frequency (STM32_PCLK_MAX)"
#endif
+/* STM32_PLLNODIV check.*/
+#if (STM32_PLLNODIV != STM32_PLLNODIV_DIV2) && \
+ (STM32_PLLNODIV != STM32_PLLNODIV_DIV1)
+#error "invalid STM32_PLLNODIV value specified"
+#endif
+
+/**
+ * @brief MCO clock before divider.
+ */
+#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_MCODIVCLK 0
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI14
+#define STM32_MCODIVCLK STM32_HSI14CLK
+#elif STM32_MCOSEL == STM32_MCOSEL_LSI
+#define STM32_MCODIVCLK STM32_LSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_LSE
+#define STM32_MCODIVCLK STM32_LSECLK
+#elif STM32_MCOSEL == STM32_MCOSEL_SYSCLK
+#define STM32_MCODIVCLK STM32_SYSCLK
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI
+#define STM32_MCODIVCLK STM32_HSICLK
+#elif STM32_MCOSEL == STM32_MCOSEL_HSE
+#define STM32_MCODIVCLK STM32_HSECLK
+#elif STM32_MCOSEL == STM32_MCOSEL_PLLDIV2
+#if STM32_PLLNODIV == STM32_PLLNODIV_DIV2
+#define STM32_MCODIVCLK (STM32_PLLCLKOUT / 2)
+#else
+#define STM32_MCODIVCLK (STM32_PLLCLKOUT / 1)
+#endif
+#elif STM32_MCOSEL == STM32_MCOSEL_HSI48
+#define STM32_MCODIVCLK STM32_HSI48CLK
+#else
+#error "invalid STM32_MCOSEL value specified"
+#endif
+
+/**
+ * @brief MCO output pin clock.
+ */
+#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCOCLK STM32_MCODIVCLK
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
+#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
+#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
+#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
+#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
+#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
+#else
+#error "invalid STM32_MCOPRE value specified"
+#endif
+
/**
* @brief RTC clock.
*/
|