diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-07 07:34:13 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2012-01-07 07:34:13 +0000 |
| commit | 7b14ebcc5f0701bc03944730ae2f3c40da0701e5 (patch) | |
| tree | c77be48c696baf3a6d4adae546229bb540e24b5b /os/hal | |
| parent | c355f186d743bc95989f447c29adcbe7c6a81dd3 (diff) | |
| download | ChibiOS-7b14ebcc5f0701bc03944730ae2f3c40da0701e5.tar.gz ChibiOS-7b14ebcc5f0701bc03944730ae2f3c40da0701e5.tar.bz2 ChibiOS-7b14ebcc5f0701bc03944730ae2f3c40da0701e5.zip | |
Fixed wrong macro prefixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3755 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/platforms/STM32F2xx/hal_lld.h | 44 | ||||
| -rw-r--r-- | os/hal/platforms/STM32F4xx/hal_lld.h | 44 |
2 files changed, 44 insertions, 44 deletions
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h index 1113ec44b..64f68b792 100644 --- a/os/hal/platforms/STM32F2xx/hal_lld.h +++ b/os/hal/platforms/STM32F2xx/hal_lld.h @@ -1164,13 +1164,13 @@ * @brief MCO1 divider clock.
*/
#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
-#define STM_MCO1DIVCLK STM32_HSICLK
+#define STM32_MCO1DIVCLK STM32_HSICLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
-#define STM_MCO1DIVCLK STM32_LSECLK
+#define STM32_MCO1DIVCLK STM32_LSECLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
-#define STM_MCO1DIVCLK STM32_HSECLK
+#define STM32_MCO1DIVCLK STM32_HSECLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
-#define STM_MCO1DIVCLK STM32_PLLCLKOUT
+#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
#else
#error "invalid STM32_MCO1SEL value specified"
#endif
@@ -1179,15 +1179,15 @@ * @brief MCO1 output pin clock.
*/
#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
-#define STM_MCO1CLK STM_MCO1DIVCLK
+#define STM32_MCO1CLK STM32_MCO1DIVCLK
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
-#define STM_MCO1CLK (STM_MCO1DIVCLK / 2)
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
-#define STM_MCO1CLK (STM_MCO1DIVCLK / 3)
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
-#define STM_MCO1CLK (STM_MCO1DIVCLK / 4)
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
-#define STM_MCO1CLK (STM_MCO1DIVCLK / 5)
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
#else
#error "invalid STM32_MCO1PRE value specified"
#endif
@@ -1196,13 +1196,13 @@ * @brief MCO2 divider clock.
*/
#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
-#define STM_MCO2DIVCLK STM32_HSECLK
+#define STM32_MCO2DIVCLK STM32_HSECLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
-#define STM_MCO2DIVCLK STM32_PLLCLKOUT
+#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
-#define STM_MCO2DIVCLK STM32_SYSCLK
+#define STM32_MCO2DIVCLK STM32_SYSCLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
-#define STM_MCO2DIVCLK STM32_PLLI2S
+#define STM32_MCO2DIVCLK STM32_PLLI2S
#else
#error "invalid STM32_MCO2SEL value specified"
#endif
@@ -1211,15 +1211,15 @@ * @brief MCO2 output pin clock.
*/
#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
-#define STM_MCO2CLK STM_MCO2DIVCLK
+#define STM32_MCO2CLK STM32_MCO2DIVCLK
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
-#define STM_MCO2CLK (STM_MCO2DIVCLK / 2)
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
-#define STM_MCO2CLK (STM_MCO2DIVCLK / 3)
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
-#define STM_MCO2CLK (STM_MCO2DIVCLK / 4)
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
-#define STM_MCO2CLK (STM_MCO2DIVCLK / 5)
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
#else
#error "invalid STM32_MCO2PRE value specified"
#endif
@@ -1248,13 +1248,13 @@ * @brief RTC clock.
*/
#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM_RTCCLK 0
+#define STM32_RTCCLK 0
#elif STM32_RTCSEL == STM32_RTCSEL_LSE
-#define STM_RTCCLK STM32_LSECLK
+#define STM32_RTCCLK STM32_LSECLK
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM_RTCCLK STM32_LSICLK
+#define STM32_RTCCLK STM32_LSICLK
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM_RTCCLK STM32_HSEDIVCLK
+#define STM32_RTCCLK STM32_HSEDIVCLK
#else
#error "invalid STM32_RTCSEL value specified"
#endif
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 43549fdd9..b55a68a4e 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -1184,13 +1184,13 @@ * @brief MCO1 divider clock.
*/
#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
-#define STM_MCO1DIVCLK STM32_HSICLK
+#define STM32_MCO1DIVCLK STM32_HSICLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
-#define STM_MCO1DIVCLK STM32_LSECLK
+#define STM32_MCO1DIVCLK STM32_LSECLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
-#define STM_MCO1DIVCLK STM32_HSECLK
+#define STM32_MCO1DIVCLK STM32_HSECLK
#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
-#define STM_MCO1DIVCLK STM32_PLLCLKOUT
+#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
#else
#error "invalid STM32_MCO1SEL value specified"
#endif
@@ -1199,15 +1199,15 @@ * @brief MCO1 output pin clock.
*/
#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
-#define STM_MCO1CLK STM_MCO1DIVCLK
+#define STM32_MCO1CLK STM32_MCO1DIVCLK
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
-#define STM_MCO1CLK (STM_MCO1DIVCLK / 2)
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
-#define STM_MCO1CLK (STM_MCO1DIVCLK / 3)
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
-#define STM_MCO1CLK (STM_MCO1DIVCLK / 4)
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
-#define STM_MCO1CLK (STM_MCO1DIVCLK / 5)
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
#else
#error "invalid STM32_MCO1PRE value specified"
#endif
@@ -1216,13 +1216,13 @@ * @brief MCO2 divider clock.
*/
#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
-#define STM_MCO2DIVCLK STM32_HSECLK
+#define STM32_MCO2DIVCLK STM32_HSECLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
-#define STM_MCO2DIVCLK STM32_PLLCLKOUT
+#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
-#define STM_MCO2DIVCLK STM32_SYSCLK
+#define STM32_MCO2DIVCLK STM32_SYSCLK
#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
-#define STM_MCO2DIVCLK STM32_PLLI2S
+#define STM32_MCO2DIVCLK STM32_PLLI2S
#else
#error "invalid STM32_MCO2SEL value specified"
#endif
@@ -1231,15 +1231,15 @@ * @brief MCO2 output pin clock.
*/
#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
-#define STM_MCO2CLK STM_MCO2DIVCLK
+#define STM32_MCO2CLK STM32_MCO2DIVCLK
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
-#define STM_MCO2CLK (STM_MCO2DIVCLK / 2)
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
-#define STM_MCO2CLK (STM_MCO2DIVCLK / 3)
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
-#define STM_MCO2CLK (STM_MCO2DIVCLK / 4)
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
-#define STM_MCO2CLK (STM_MCO2DIVCLK / 5)
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
#else
#error "invalid STM32_MCO2PRE value specified"
#endif
@@ -1268,13 +1268,13 @@ * @brief RTC clock.
*/
#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM_RTCCLK 0
+#define STM32_RTCCLK 0
#elif STM32_RTCSEL == STM32_RTCSEL_LSE
-#define STM_RTCCLK STM32_LSECLK
+#define STM32_RTCCLK STM32_LSECLK
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM_RTCCLK STM32_LSICLK
+#define STM32_RTCCLK STM32_LSICLK
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM_RTCCLK STM32_HSEDIVCLK
+#define STM32_RTCCLK STM32_HSEDIVCLK
#else
#error "invalid STM32_RTCSEL value specified"
#endif
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