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authorbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-07-12 18:34:11 +0000
committerbarthess <barthess@35acf78f-673a-0410-8e92-d51de3d6d3f4>2011-07-12 18:34:11 +0000
commit71ebbf914fa1cf07e969bdf774a861a4d76d0b9a (patch)
treed4a7e23f98b5e9439424f11190fb7dde4f43c4ea /os/hal
parent621d794bf0d2a6456221f1e478de66e48c293063 (diff)
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I2C. Comments cleanups.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3154 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
-rw-r--r--os/hal/platforms/STM32/i2c_lld.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c
index 1b36fde8f..594f833a1 100644
--- a/os/hal/platforms/STM32/i2c_lld.c
+++ b/os/hal/platforms/STM32/i2c_lld.c
@@ -154,8 +154,9 @@ void _i2c_ev7_master_rec_byte_qued(I2CDriver *i2cp){
break;
case I2C_FLG_MASTER_RECEIVER:
- /* some time in hi load cases possible to miss interrupt
- * ??? TODO: really?*/
+ /* Some times in hi load scenarions it is possible to "miss" interrupt
+ * because STM32 I2C has OR'ed interrupt sources. This case handle that
+ * scenario. */
if (i2cp->rxbytes > 3){
*rxBuffp = dp->DR;
rxBuffp++;