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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-11-26 21:26:48 +0000 |
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| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2011-11-26 21:26:48 +0000 |
| commit | 6d11e44877536fd464bf6afd18b35bb17187f480 (patch) | |
| tree | 46c29eedf1a0e876f29cea48261aa72951d7a7d9 /os/hal | |
| parent | 98807ccef14218336bc10b1d17f3d4404949250d (diff) | |
| download | ChibiOS-6d11e44877536fd464bf6afd18b35bb17187f480.tar.gz ChibiOS-6d11e44877536fd464bf6afd18b35bb17187f480.tar.bz2 ChibiOS-6d11e44877536fd464bf6afd18b35bb17187f480.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3533 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/platforms/STM32F4xx/hal_lld.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index a4dd1b775..0650c84f8 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -212,11 +212,11 @@ #define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
-#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
-#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
-#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
-#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
-#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
+#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */
+#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */
+#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */
+#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */
+#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */
/**
* @name RCC_PLLI2SCFGR register bits definitions
|