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authorGiovanni Di Sirio <gdisirio@gmail.com>2018-12-08 09:17:09 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2018-12-08 09:17:09 +0000
commit53093a74b030cffbb4ebd78adaa4707ea4ecf9db (patch)
treed0ee4a391a27a85900703a1a7f345febeb57da4a /os/hal
parent426d45d6d42e6f45a92b9db8d4c89291c3781e85 (diff)
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Added missing macros.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12462 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal')
-rw-r--r--os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h28
-rw-r--r--os/hal/ports/STM32/STM32L4xx+/stm32_registry.h11
2 files changed, 37 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h b/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h
index b8c367768..76f842ccc 100644
--- a/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32L4xx+/stm32_rcc.h
@@ -1263,6 +1263,34 @@
#define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST)
/** @} */
+/**
+ * @name DCMI peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the DCMI peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDCMI(lp) rccEnableAHB2(RCC_AHB2ENR_DCMIEN, lp)
+
+/**
+ * @brief Disables the DCMI peripheral clock.
++ *
++ * @api
+ */
+#define rccDisableDCMI() rccDisableAHB2(RCC_AHB2ENR_DCMIEN)
+
+/**
+ * @brief Resets the DCMI peripheral.
+ *
+ * @api
+ */
+#define rccResetDCMI() rccResetAHB2(RCC_AHB2RSTR_DCMIRST)
+/** @} */
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h
index f6d316137..2e0b885b7 100644
--- a/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L4xx+/stm32_registry.h
@@ -380,10 +380,12 @@
#define STM32_IWDG_IS_WINDOWED TRUE
/* LTDC attributes.*/
-#define STM32_HAS_LTDC FALSE
+#define STM32_HAS_LTDC TRUE
/* DMA2D attributes.*/
-#define STM32_HAS_DMA2D FALSE
+#define STM32_HAS_DMA2D TRUE
+#define STM32_DMA2D_NUMBER 90
+#define STM32_DMA2D_HANDLER Vector1A8
/* FSMC attributes.*/
#define STM32_HAS_FSMC TRUE
@@ -392,6 +394,11 @@
#define STM32_HAS_CRC TRUE
#define STM32_CRC_PROGRAMMABLE TRUE
+/* DCMI attributes.*/
+#define STM32_HAS_DCMI TRUE
+#define STM32_DCMI_NUMBER 85
+#define STM32_DCMI_HANDLER Vector14C
+
#endif /* defined(STM32L4R5xx) || defined(STM32L4R7xx) ||
defined(STM32L4R9xx) || defined(STM32L4S5xx) ||
defined(STM32L4S7xx) || defined(STM32L4S9xx) */