Tentative fix for shared timer IRQs, not complete.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12524 110e8d01-0319-4d1e-a829-52ad28d1bb01

4 files changed, 437 insertions, 16 deletions

diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c
index f943a567c..a25edc9f9 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.c
@@ -131,6 +131,30 @@ GPTDriver GPTD14;
 #endif

 

 /**

+ * @brief   GPTD15 driver identifier.

+ * @note    The driver GPTD14 allocates the timer TIM14 when enabled.

+ */

+#if STM32_GPT_USE_TIM15 || defined(__DOXYGEN__)

+GPTDriver GPTD15;

+#endif

+

+/**

+ * @brief   GPTD16 driver identifier.

+ * @note    The driver GPTD14 allocates the timer TIM14 when enabled.

+ */

+#if STM32_GPT_USE_TIM16 || defined(__DOXYGEN__)

+GPTDriver GPTD16;

+#endif

+

+/**

+ * @brief   GPTD17 driver identifier.

+ * @note    The driver GPTD14 allocates the timer TIM14 when enabled.

+ */

+#if STM32_GPT_USE_TIM17 || defined(__DOXYGEN__)

+GPTDriver GPTD17;

+#endif

+

+/**

  * @brief   GPTD21 driver identifier.

  * @note    The driver GPTD21 allocates the timer TIM21 when enabled.

  */

@@ -164,7 +188,7 @@ GPTDriver GPTD22;
 #error "STM32_TIM1_UP_HANDLER not defined"

 #endif

 /**

- * @brief   TIM2 interrupt handler.

+ * @brief   TIM1 interrupt handler.

  *

  * @isr

  */

@@ -410,6 +434,24 @@ OSAL_IRQ_HANDLER(STM32_TIM14_HANDLER) {
 #endif /* !defined(STM32_TIM14_SUPPRESS_ISR) */

 #endif /* STM32_GPT_USE_TIM14 */

 

+#if STM32_GPT_USE_TIM15 || defined(__DOXYGEN__)

+#if !defined(STM32_TIM15_SUPPRESS_ISR)

+#error "TIM15 ISR not defined by platform"

+#endif /* !defined(STM32_TIM15_SUPPRESS_ISR) */

+#endif /* STM32_GPT_USE_TIM15 */

+

+#if STM32_GPT_USE_TIM16 || defined(__DOXYGEN__)

+#if !defined(STM32_TIM16_SUPPRESS_ISR)

+#error "TIM16 ISR not defined by platform"

+#endif /* !defined(STM32_TIM16_SUPPRESS_ISR) */

+#endif /* STM32_GPT_USE_TIM16 */

+

+#if STM32_GPT_USE_TIM17 || defined(__DOXYGEN__)

+#if !defined(STM32_TIM17_SUPPRESS_ISR)

+#error "TIM17 ISR not defined by platform"

+#endif /* !defined(STM32_TIM17_SUPPRESS_ISR) */

+#endif /* STM32_GPT_USE_TIM17 */

+

 #if STM32_GPT_USE_TIM21 || defined(__DOXYGEN__)

 #if !defined(STM32_TIM21_SUPPRESS_ISR)

 #if !defined(STM32_TIM21_HANDLER)

@@ -535,6 +577,24 @@ void gpt_lld_init(void) {
   gptObjectInit(&GPTD14);

 #endif

 

+#if STM32_GPT_USE_TIM15

+  /* Driver initialization.*/

+  GPTD15.tim = STM32_TIM15;

+  gptObjectInit(&GPTD15);

+#endif

+

+#if STM32_GPT_USE_TIM16

+  /* Driver initialization.*/

+  GPTD16.tim = STM32_TIM16;

+  gptObjectInit(&GPTD16);

+#endif

+

+#if STM32_GPT_USE_TIM17

+  /* Driver initialization.*/

+  GPTD17.tim = STM32_TIM17;

+  gptObjectInit(&GPTD17);

+#endif

+

 #if STM32_GPT_USE_TIM21

   /* Driver initialization.*/

   GPTD21.tim = STM32_TIM21;

@@ -740,6 +800,54 @@ void gpt_lld_start(GPTDriver *gptp) {
     }

 #endif

 

+#if STM32_GPT_USE_TIM15

+    if (&GPTD15 == gptp) {

+      rccEnableTIM15(true);

+      rccResetTIM15();

+#if defined(STM32_TIM15CLK)

+      gptp->clock = STM32_TIM15CLK;

+#else

+      gptp->clock = STM32_TIMCLK2;

+#endif

+    }

+#endif

+

+#if STM32_GPT_USE_TIM15

+    if (&GPTD15 == gptp) {

+      rccEnableTIM15(true);

+      rccResetTIM15();

+#if defined(STM32_TIM15CLK)

+      gptp->clock = STM32_TIM15CLK;

+#else

+      gptp->clock = STM32_TIMCLK2;

+#endif

+    }

+#endif

+

+#if STM32_GPT_USE_TIM16

+    if (&GPTD16 == gptp) {

+      rccEnableTIM16(true);

+      rccResetTIM16();

+#if defined(STM32_TIM16CLK)

+      gptp->clock = STM32_TIM16CLK;

+#else

+      gptp->clock = STM32_TIMCLK2;

+#endif

+    }

+#endif

+

+#if STM32_GPT_USE_TIM17

+    if (&GPTD17 == gptp) {

+      rccEnableTIM17(true);

+      rccResetTIM17();

+#if defined(STM32_TIM17CLK)

+      gptp->clock = STM32_TIM17CLK;

+#else

+      gptp->clock = STM32_TIMCLK2;

+#endif

+    }

+#endif

+

 #if STM32_GPT_USE_TIM21

     if (&GPTD21 == gptp) {

       rccEnableTIM21(true);

@@ -907,6 +1015,24 @@ void gpt_lld_stop(GPTDriver *gptp) {
     }

 #endif

 

+#if STM32_GPT_USE_TIM15

+    if (&GPTD15 == gptp) {

+      rccDisableTIM15();

+    }

+#endif

+

+#if STM32_GPT_USE_TIM16

+    if (&GPTD16 == gptp) {

+      rccDisableTIM16();

+    }

+#endif

+

+#if STM32_GPT_USE_TIM17

+    if (&GPTD17 == gptp) {

+      rccDisableTIM17();

+    }

+#endif

+

 #if STM32_GPT_USE_TIM21

     if (&GPTD21 == gptp) {

 #if !defined(STM32_TIM21_SUPPRESS_ISR)

diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.h b/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.h
index 1bc048c19..945110b9b 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.h
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_gpt_lld.h
@@ -150,6 +150,33 @@
 #endif

 

 /**

+ * @brief   GPTD14 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD15 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM15) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM15                 FALSE

+#endif

+

+/**

+ * @brief   GPTD14 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD16 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM16) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM16                 FALSE

+#endif

+

+/**

+ * @brief   GPTD14 driver enable switch.

+ * @details If set to @p TRUE the support for GPTD17 is included.

+ * @note    The default is @p TRUE.

+ */

+#if !defined(STM32_GPT_USE_TIM17) || defined(__DOXYGEN__)

+#define STM32_GPT_USE_TIM17                 FALSE

+#endif

+

+/**

  * @brief   GPTD21 driver enable switch.

  * @details If set to @p TRUE the support for GPTD21 is included.

  * @note    The default is @p TRUE.

@@ -252,6 +279,27 @@
 #endif

 

 /**

+ * @brief   GPTD15 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM15_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM15_IRQ_PRIORITY        7

+#endif

+

+/**

+ * @brief   GPTD16 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM16_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM16_IRQ_PRIORITY        7

+#endif

+

+/**

+ * @brief   GPTD17 interrupt priority level setting.

+ */

+#if !defined(STM32_GPT_TIM17_IRQ_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_GPT_TIM17_IRQ_PRIORITY        7

+#endif

+

+/**

  * @brief   GPTD21 interrupt priority level setting.

  */

 #if !defined(STM32_GPT_TIM21_IRQ_PRIORITY) || defined(__DOXYGEN__)

@@ -314,6 +362,18 @@
 #define STM32_HAS_TIM14                     FALSE

 #endif

 

+#if !defined(STM32_HAS_TIM15)

+#define STM32_HAS_TIM15                     FALSE

+#endif

+

+#if !defined(STM32_HAS_TIM16)

+#define STM32_HAS_TIM16                     FALSE

+#endif

+

+#if !defined(STM32_HAS_TIM17)

+#define STM32_HAS_TIM17                     FALSE

+#endif

+

 #if !defined(STM32_HAS_TIM21)

 #define STM32_HAS_TIM21                     FALSE

 #endif

@@ -370,20 +430,34 @@
 #error "TIM14 not present in the selected device"

 #endif

 

+#if STM32_GPT_USE_TIM15 && !STM32_HAS_TIM15

+#error "TIM15 not present in the selected device"

+#endif

+

+#if STM32_GPT_USE_TIM16 && !STM32_HAS_TIM16

+#error "TIM16 not present in the selected device"

+#endif

+

+#if STM32_GPT_USE_TIM17 && !STM32_HAS_TIM17

+#error "TIM17 not present in the selected device"

+#endif

+

 #if STM32_GPT_USE_TIM21 && !STM32_HAS_TIM21

-#error "TIM14 not present in the selected device"

+#error "TIM21 not present in the selected device"

 #endif

 

 #if STM32_GPT_USE_TIM22 && !STM32_HAS_TIM22

-#error "TIM14 not present in the selected device"

+#error "TIM22 not present in the selected device"

 #endif

 

 #if !STM32_GPT_USE_TIM1 && !STM32_GPT_USE_TIM2 &&                           \

-    !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 &&  \

-    !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM6 &&  \

-    !STM32_GPT_USE_TIM7 && !STM32_GPT_USE_TIM8 &&  \

-    !STM32_GPT_USE_TIM9 && !STM32_GPT_USE_TIM11 && \

-    !STM32_GPT_USE_TIM12 && !STM32_GPT_USE_TIM14 && \

+    !STM32_GPT_USE_TIM3 && !STM32_GPT_USE_TIM4 &&                           \

+    !STM32_GPT_USE_TIM5 && !STM32_GPT_USE_TIM6 &&                           \

+    !STM32_GPT_USE_TIM7 && !STM32_GPT_USE_TIM8 &&                           \

+    !STM32_GPT_USE_TIM9 && !STM32_GPT_USE_TIM11 &&                          \

+    !STM32_GPT_USE_TIM12 && !STM32_GPT_USE_TIM14 &&                         \

+    !STM32_GPT_USE_TIM15 && !STM32_GPT_USE_TIM16 &&                         \

+    !STM32_GPT_USE_TIM17 &&                                                 \

     !STM32_GPT_USE_TIM21 && !STM32_GPT_USE_TIM22

 #error "GPT driver activated but no TIM peripheral assigned"

 #endif

@@ -485,6 +559,30 @@
 #endif

 #endif

 

+#if STM32_GPT_USE_TIM15

+#if defined(STM32_TIM15_IS_USED)

+#error "GPTD14 requires TIM15 but the timer is already used"

+#else

+#define STM32_TIM15_IS_USED

+#endif

+#endif

+

+#if STM32_GPT_USE_TIM16

+#if defined(STM32_TIM16_IS_USED)

+#error "GPTD14 requires TIM16 but the timer is already used"

+#else

+#define STM32_TIM16_IS_USED

+#endif

+#endif

+

+#if STM32_GPT_USE_TIM17

+#if defined(STM32_TIM17_IS_USED)

+#error "GPTD14 requires TIM17 but the timer is already used"

+#else

+#define STM32_TIM17_IS_USED

+#endif

+#endif

+

 #if STM32_GPT_USE_TIM21

 #if defined(STM32_TIM21_IS_USED)

 #error "GPTD21 requires TIM21 but the timer is already used"

@@ -562,6 +660,21 @@
 #error "Invalid IRQ priority assigned to TIM14"

 #endif

 

+#if STM32_GPT_USE_TIM15 && !defined(STM32_TIM15_SUPPRESS_ISR) &&            \

+    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM15_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIM15"

+#endif

+

+#if STM32_GPT_USE_TIM16 && !defined(STM32_TIM16_SUPPRESS_ISR) &&            \

+    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM16_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIM16"

+#endif

+

+#if STM32_GPT_USE_TIM17 && !defined(STM32_TIM17_SUPPRESS_ISR) &&            \

+    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM17_IRQ_PRIORITY)

+#error "Invalid IRQ priority assigned to TIM17"

+#endif

+

 #if STM32_GPT_USE_TIM21 && !defined(STM32_TIM21_SUPPRESS_ISR) &&            \

     !OSAL_IRQ_IS_VALID_PRIORITY(STM32_GPT_TIM21_IRQ_PRIORITY)

 #error "Invalid IRQ priority assigned to TIM21"

@@ -739,6 +852,18 @@ extern GPTDriver GPTD12;
 extern GPTDriver GPTD14;

 #endif

 

+#if STM32_GPT_USE_TIM15 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD15;

+#endif

+

+#if STM32_GPT_USE_TIM16 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD16;

+#endif

+

+#if STM32_GPT_USE_TIM17 && !defined(__DOXYGEN__)

+extern GPTDriver GPTD17;

+#endif

+

 #if STM32_GPT_USE_TIM21 && !defined(__DOXYGEN__)

 extern GPTDriver GPTD21;

 #endif

diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_isr.c b/os/hal/ports/STM32/STM32F3xx/stm32_isr.c
index 674cd0481..384f0815c 100644
--- a/os/hal/ports/STM32/STM32F3xx/stm32_isr.c
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_isr.c
@@ -209,9 +209,129 @@ OSAL_IRQ_HANDLER(VectorE0) {
   OSAL_IRQ_EPILOGUE();

 }

 #endif

-

 #endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */

 

+#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)

+/**

+ * @brief   TIM1-BRK, TIM15 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorA0) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+#if STM32_GPT_USE_TIM15

+  gpt_lld_serve_interrupt(&GPTD15);

+#endif

+#endif

+#if HAL_USE_ICU

+#if STM32_ICU_USE_TIM15

+  icu_lld_serve_interrupt(&ICUD15);

+#endif

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM15

+  pwm_lld_serve_interrupt(&PWMD15);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   TIM1-UP, TIM16 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorA4) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+#if STM32_GPT_USE_TIM1

+  gpt_lld_serve_interrupt(&GPTD1);

+#endif

+#if STM32_GPT_USE_TIM16

+  gpt_lld_serve_interrupt(&GPTD16);

+#endif

+#endif

+#if HAL_USE_ICU

+#if STM32_ICU_USE_TIM1

+  icu_lld_serve_interrupt(&ICUD1);

+#endif

+#if STM32_ICU_USE_TIM16

+  icu_lld_serve_interrupt(&ICUD16);

+#endif

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM1

+  pwm_lld_serve_interrupt(&PWMD1);

+#endif

+#if STM32_PWM_USE_TIM16

+  pwm_lld_serve_interrupt(&PWMD16);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   TIM1-TRG-COM, TIM17 interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorA8) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+#if STM32_GPT_USE_TIM17

+  gpt_lld_serve_interrupt(&GPTD17);

+#endif

+#endif

+#if HAL_USE_ICU

+#if STM32_ICU_USE_TIM17

+  icu_lld_serve_interrupt(&ICUD17);

+#endif

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM17

+  pwm_lld_serve_interrupt(&PWMD17);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+

+/**

+ * @brief   TIM1-CC interrupt handler.

+ *

+ * @isr

+ */

+OSAL_IRQ_HANDLER(VectorAC) {

+

+  OSAL_IRQ_PROLOGUE();

+

+#if HAL_USE_GPT

+  /* Not used by GPT.*/

+#endif

+#if HAL_USE_ICU

+#if STM32_ICU_USE_TIM1

+  icu_lld_serve_interrupt(&ICUD1);

+#endif

+#endif

+#if HAL_USE_PWM

+#if STM32_PWM_USE_TIM1

+  pwm_lld_serve_interrupt(&PWMD1);

+#endif

+#endif

+

+  OSAL_IRQ_EPILOGUE();

+}

+#endif /* HAL_USE_GPT */

+

 /*===========================================================================*/

 /* Driver exported functions.                                                */

 /*===========================================================================*/

@@ -224,13 +344,19 @@ OSAL_IRQ_HANDLER(VectorE0) {
 void irqInit(void) {

 

 #if HAL_USE_PAL

-  nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY);

-  nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY);

-  nvicEnableVector(EXTI2_TSC_IRQn, STM32_IRQ_EXTI2_PRIORITY);

-  nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY);

-  nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY);

-  nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY);

-  nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY);

+  nvicEnableVector(EXTI0_IRQn,              STM32_IRQ_EXTI0_PRIORITY);

+  nvicEnableVector(EXTI1_IRQn,              STM32_IRQ_EXTI1_PRIORITY);

+  nvicEnableVector(EXTI2_TSC_IRQn,          STM32_IRQ_EXTI2_PRIORITY);

+  nvicEnableVector(EXTI3_IRQn,              STM32_IRQ_EXTI3_PRIORITY);

+  nvicEnableVector(EXTI4_IRQn,              STM32_IRQ_EXTI4_PRIORITY);

+  nvicEnableVector(EXTI9_5_IRQn,            STM32_IRQ_EXTI5_9_PRIORITY);

+  nvicEnableVector(EXTI15_10_IRQn,          STM32_IRQ_EXTI10_15_PRIORITY);

+#endif

+#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)

+  nvicEnableVector(TIM1_BRK_TIM15_IRQn,     STM32_IRQ_TIM1_BRK_TIM15_PRIORITY);

+  nvicEnableVector(TIM1_UP_TIM16_IRQn,      STM32_IRQ_TIM1_UP_TIM16_PRIORITY);

+  nvicEnableVector(TIM1_TRG_COM_TIM17_IRQn, STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY);

+  nvicEnableVector(TIM1_CC_IRQn,            STM32_IRQ_TIM1_CC_PRIORITY);

 #endif

 }

 

@@ -250,6 +376,12 @@ void irqDeinit(void) {
   nvicDisableVector(EXTI9_5_IRQn);

   nvicDisableVector(EXTI15_10_IRQn);

 #endif

+#if HAL_USE_GPT || HAL_USE_ICU || HAL_USE_PWM || defined(__DOXYGEN__)

+  nvicDisableVector(TIM1_BRK_TIM15_IRQn);

+  nvicDisableVector(TIM1_UP_TIM16_IRQn);

+  nvicDisableVector(TIM1_TRG_COM_TIM17_IRQn);

+  nvicDisableVector(TIM1_CC_IRQn);

+#endif

 }

 

 /** @} */

diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
index 9917b993f..03d87e5e0 100644
--- a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
@@ -30,6 +30,16 @@
 /*===========================================================================*/

 

 /**

+ * @name    ISRs suppressed in standard drivers

+ * @{

+ */

+#define STM32_TIM1_SUPPRESS_ISR

+#define STM32_TIM15_SUPPRESS_ISR

+#define STM32_TIM16_SUPPRESS_ISR

+#define STM32_TIM17_SUPPRESS_ISR

+/** @} */

+

+/**

  * @name    ISR names and numbers remapping

  * @{

  */

@@ -253,6 +263,34 @@
 #if !defined(STM32_IRQ_EXTI33_PRIORITY) || defined(__DOXYGEN__)

 #define STM32_IRQ_EXTI33_PRIORITY           6

 #endif

+

+/**

+ * @brief   TIM1-BRK, TIM15 interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_BRK_TIM15_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY   7

+#endif

+

+/**

+ * @brief   TIM1-UP, TIM16 interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_UP_TIM16_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY    7

+#endif

+

+/**

+ * @brief   TIM1-TRG-COM, TIM17 interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7

+#endif

+

+/**

+ * @brief   TIM1-CC interrupt priority level setting.

+ */

+#if !defined(STM32_IRQ_TIM1_CC_PRIORITY) || defined(__DOXYGEN__)

+#define STM32_IRQ_TIM1_CC_PRIORITY          7

+#endif

 /** @} */

 

 /*===========================================================================*/