RTC. Merge RTC code from trunk.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/rtc_dev@3595 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 21 insertions, 10 deletions

diff --git a/os/hal/platforms/STM32/RTCv1/rtc_lld.c b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
index cae23525f..1a6c85d8b 100644
--- a/os/hal/platforms/STM32/RTCv1/rtc_lld.c
+++ b/os/hal/platforms/STM32/RTCv1/rtc_lld.c
@@ -132,13 +132,14 @@ void rtc_lld_init(void){
   }

 

 #if STM32_RTC == STM32_RTC_LSE

+#define RTC_CLK   STM32_LSECLK

   if (!(RCC->BDCR & RCC_BDCR_LSEON)) {

     RCC->BDCR |= RCC_BDCR_LSEON;

     while (!(RCC->BDCR & RCC_BDCR_LSERDY))

       ;

   }

-  preload = STM32_LSECLK - 1;

 #elif STM32_RTC == STM32_RTC_LSI

+#define RTC_CLK   STM32_LSICLK

   /* TODO: Move the LSI clock initialization in the HAL low level driver.*/

   RCC->CSR |= RCC_CSR_LSION;

   while (!(RCC->CSR & RCC_CSR_LSIRDY))

@@ -146,14 +147,15 @@ void rtc_lld_init(void){
   /* According to errata sheet we must wait additional 100 uS for

      stabilization.

      TODO: Change this code, software loops are not reliable.*/

-  uint32_t tmo = (STM32_SYSCLK / 1000000) * 100;

+  volatile uint32_t tmo = (STM32_SYSCLK / 1000000) * 100;

   while (tmo--)

     ;

-  preload = STM32_LSICLK - 1;

 #elif STM32_RTC == STM32_RTC_HSE

-  preload = (STM32_HSICLK / 128) - 1;

+#define RTC_CLK   (STM32_HSECLK / 128)

 #endif

 

+  preload = RTC_CLK - 1;

+

   /* Selects clock source (previously enabled and stabilized).*/

   RCC->BDCR = (RCC->BDCR & ~RCC_BDCR_RTCSEL) | STM32_RTC;

 

@@ -213,19 +215,28 @@ void rtc_lld_set_time(RTCDriver *rtcp, const RTCTime *timespec) {
  * @brief   Get current time.

  *

  * @param[in] rtcp      pointer to RTC driver structure

- * @param[out] timespec pointer to a @p RTCTime structure

+ * @param[in] timespec  pointer to a @p RTCTime structure

  *

  * @notapi

  */

 void rtc_lld_get_time(RTCDriver *rtcp, RTCTime *timespec) {

-  uint32_t time_frac;

-

   (void)rtcp;

 

+  uint32_t time_frac;

+

+READ_REGISTERS:

+  chSysLock();

+  timespec->tv_sec = ((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL;

   time_frac = (((uint32_t)RTC->DIVH) << 16) + (uint32_t)RTC->DIVL;

-  timespec->tv_msec = (uint16_t)(((STM32_LSECLK - time_frac) * 1000) /

-                                 STM32_LSECLK);

-  timespec->tv_sec = (RTC->CNTH << 16) + RTC->CNTL;

+  chSysUnlock();

+

+  /* If second counter updated between reading of integer and fractional parts

+   * we must reread both values. */

+  if((timespec->tv_sec) != (((uint32_t)(RTC->CNTH) << 16) + RTC->CNTL)){

+    goto READ_REGISTERS;

+  }

+

+  timespec->tv_msec = (uint16_t)(((RTC_CLK - 1 - time_frac) * 1000) / RTC_CLK);

 }

 

 /**