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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-07-28 09:42:11 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-07-28 09:42:11 +0000 |
| commit | 11db006b0f112325b4bc0ccc3e4c7c3c4ab87bcf (patch) | |
| tree | 79e0559935a5fc5f5a7fc6cf162d1a958eb3db18 /os/hal | |
| parent | cc826010ae690e91d8bd36ca3abccd8dc27a139f (diff) | |
| download | ChibiOS-11db006b0f112325b4bc0ccc3e4c7c3c4ab87bcf.tar.gz ChibiOS-11db006b0f112325b4bc0ccc3e4c7c3c4ab87bcf.tar.bz2 ChibiOS-11db006b0f112325b4bc0ccc3e4c7c3c4ab87bcf.zip | |
Fixed bugs #969 and #970.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12205 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal')
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.c | 3 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.h | 6 |
2 files changed, 6 insertions, 3 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index a144142bb..fa02600af 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -92,6 +92,9 @@ static void hal_lld_backup_domain_init(void) { RCC->BDCR |= RCC_BDCR_RTCEN;
}
#endif /* HAL_USE_RTC */
+
+ /* Low speed output mode.*/
+ RCC->BDCR |= STM32_LSCOSEL;
}
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.h b/os/hal/ports/STM32/STM32L4xx/hal_lld.h index 3722fd0ee..c792a9313 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.h @@ -291,7 +291,7 @@ #define STM32_SWPMI1SEL_HSI16 (1 << 30) /**< SWPMI1 source is HSI16. */
#define STM32_DFSDMSEL_MASK (1 << 31) /**< DFSDMSEL mask. */
-#define STM32_DFSDMSEL_PCLK1 (0 << 31) /**< DFSDM source is PCLK1. */
+#define STM32_DFSDMSEL_PCLK2 (0 << 31) /**< DFSDM source is PCLK2. */
#define STM32_DFSDMSEL_SYSCLK (1 << 31) /**< DFSDM source is SYSCLK. */
/** @} */
@@ -2130,8 +2130,8 @@ /**
* @brief DFSDM clock frequency.
*/
-#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK1) || defined(__DOXYGEN__)
-#define STM32_DFSDMCLK STM32_PCLK1
+#if (STM32_DFSDMSEL == STM32_DFSDMSEL_PCLK2) || defined(__DOXYGEN__)
+#define STM32_DFSDMCLK STM32_PCLK2
#elif STM32_DFSDMSEL == STM32_DFSDMSEL_SYSCLK
#define STM32_DFSDMCLK STM32_SYSCLK
#else
|