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authorgdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-04-18 18:41:50 +0000
committergdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>2012-04-18 18:41:50 +0000
commit0c9da34878eb91bc9ce3a7e98464bcdddaae2000 (patch)
tree24d3c310cf06782b1a603198844abb8d9129ab12 /os/hal
parent2446f558dbb555da50a0d76e28ee148f4ee564bd (diff)
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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4116 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal')
-rw-r--r--os/hal/platforms/STM32/sdc_lld.c17
1 files changed, 7 insertions, 10 deletions
diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c
index 953f42d32..59f988eb0 100644
--- a/os/hal/platforms/STM32/sdc_lld.c
+++ b/os/hal/platforms/STM32/sdc_lld.c
@@ -176,26 +176,23 @@ static bool_t sdc_lld_wait_transaction_end(SDCDriver *sdcp, uint32_t n,
return CH_FAILED;
}
- /* Wait until DMA channel enabled to be sure that all data transferred.*/
- while (sdcp->dma->stream->CR & STM32_DMA_CR_EN)
- ;
-
- /* DMA event flags must be manually cleared.*/
- dmaStreamClearInterrupt(sdcp->dma);
+ /* Waits for transfer completion at DMA level, the the stream is
+ disabled and cleared.*/
+ dmaWaitCompletion(sdcp->dma);
SDIO->ICR = STM32_SDIO_ICR_ALL_FLAGS;
SDIO->DCTRL = 0;
chSysUnlock();
/* Wait until interrupt flags to be cleared.*/
- while (((DMA2->LISR) >> (sdcp->dma->ishift)) & STM32_DMA_ISR_TCIF)
- dmaStreamClearInterrupt(sdcp->dma);
+/* while (((DMA2->LISR) >> (sdcp->dma->ishift)) & STM32_DMA_ISR_TCIF)
+ dmaStreamClearInterrupt(sdcp->dma);*/
/* Finalize transaction.*/
if (n > 1)
return sdc_lld_send_cmd_short_crc(sdcp, SDC_CMD_STOP_TRANSMISSION, 0, resp);
- else
- return CH_SUCCESS;
+
+ return CH_SUCCESS;
}
/**