DMA and SPI code, not complete.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11200 35acf78f-673a-0410-8e92-d51de3d6d3f4

5 files changed, 69 insertions, 266 deletions

diff --git a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h
index 3d8c08f13..9c4302cc4 100644
--- a/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h
+++ b/os/hal/ports/STM32/LLD/DMAv3/stm32_dma.h
@@ -48,16 +48,6 @@
 #define STM32_DMA_ISR_MASK          0x3DU

 

 /**

- * @brief   Returns the channel associated to the specified stream.

- *

- * @param[in] id        the unique numeric stream identifier

- * @param[in] c         a stream/channel association word, one channel per

- *                      nibble

- * @return              Returns the channel associated to the stream.

- */

-#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7U) * 4U)) & 15U)

-

-/**

  * @brief   Checks if a DMA priority is within the valid range.

  * @param[in] prio      DMA priority

  *

@@ -68,37 +58,6 @@
 #define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))

 

 /**

- * @brief   Returns an unique numeric identifier for a DMA stream.

- *

- * @param[in] dma       the DMA unit number

- * @param[in] stream    the stream number

- * @return              An unique numeric stream identifier.

- */

-#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1U) * 8U) + (stream))

-

-/**

- * @brief   Returns a DMA stream identifier mask.

- *

- *

- * @param[in] dma       the DMA unit number

- * @param[in] stream    the stream number

- * @return              A DMA stream identifier mask.

- */

-#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \

-  (1U << STM32_DMA_STREAM_ID(dma, stream))

-

-/**

- * @brief   Checks if a DMA stream unique identifier belongs to a mask.

- * @param[in] id        the stream numeric identifier

- * @param[in] mask      the stream numeric identifiers mask

- *

- * @retval              The check result.

- * @retval FALSE        id does not belong to the mask.

- * @retval TRUE         id belongs to the mask.

- */

-#define STM32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))

-

-/**

  * @name    DMA streams identifiers

  * @{

  */

@@ -135,66 +94,58 @@
  */

 #define STM32_DMA_CR_RESET_VALUE    0x00000000U

 #define STM32_DMA_CR_EN             DMA_SxCR_EN

+#define STM32_DMA_CR_DMEIE          DMA_SxCR_DMEIE

 #define STM32_DMA_CR_TEIE           DMA_SxCR_TEIE

 #define STM32_DMA_CR_HTIE           DMA_SxCR_HTIE

 #define STM32_DMA_CR_TCIE           DMA_SxCR_TCIE

-#define STM32_DMA_CR_DIR_MASK       DMA_SxCR_DIR

+#define STM32_DMA_CR_PFCTRL         DMA_SxCR_PFCTRL

+#define STM32_DMA_CR_DIR_MASK       DMA_SxCR_DIR_Msk

 #define STM32_DMA_CR_DIR_P2M        0

 #define STM32_DMA_CR_DIR_M2P        DMA_SxCR_DIR_0

 #define STM32_DMA_CR_DIR_M2M        DMA_SxCR_DIR_1

 #define STM32_DMA_CR_CIRC           DMA_SxCR_CIRC

 #define STM32_DMA_CR_PINC           DMA_SxCR_PINC

 #define STM32_DMA_CR_MINC           DMA_SxCR_MINC

-#define STM32_DMA_CR_PSIZE_MASK     DMA_SxCR_PSIZE

+#define STM32_DMA_CR_PSIZE_MASK     DMA_SxCR_PSIZE_Msk

 #define STM32_DMA_CR_PSIZE_BYTE     0

 #define STM32_DMA_CR_PSIZE_HWORD    DMA_SxCR_PSIZE_0

 #define STM32_DMA_CR_PSIZE_WORD     DMA_SxCR_PSIZE_1

-#define STM32_DMA_CR_MSIZE_MASK     DMA_SxCR_MSIZE

+#define STM32_DMA_CR_MSIZE_MASK     DMA_SxCR_MSIZE_Msk

 #define STM32_DMA_CR_MSIZE_BYTE     0

 #define STM32_DMA_CR_MSIZE_HWORD    DMA_SxCR_MSIZE_0

 #define STM32_DMA_CR_MSIZE_WORD     DMA_SxCR_MSIZE_1

 #define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \

                                      STM32_DMA_CR_MSIZE_MASK)

-#define STM32_DMA_CR_PL_MASK        DMA_SxCR_PL

-#define STM32_DMA_CR_PL(n)          ((n) << 16U)

-/** @} */

-

-/**

- * @name    CR register constants only found in STM32F2xx/STM32F4xx

- * @{

- */

-#define STM32_DMA_CR_DMEIE          DMA_SxCR_DMEIE

-#define STM32_DMA_CR_PFCTRL         DMA_SxCR_PFCTRL

 #define STM32_DMA_CR_PINCOS         DMA_SxCR_PINCOS

+#define STM32_DMA_CR_PL_MASK        DMA_SxCR_PL_Msk

+#define STM32_DMA_CR_PL(n)          ((n) << 16U)

 #define STM32_DMA_CR_DBM            DMA_SxCR_DBM

 #define STM32_DMA_CR_CT             DMA_SxCR_CT

-#define STM32_DMA_CR_PBURST_MASK    DMA_SxCR_PBURST

+#define STM32_DMA_CR_PBURST_MASK    DMA_SxCR_PBURST_Msk

 #define STM32_DMA_CR_PBURST_SINGLE  0

 #define STM32_DMA_CR_PBURST_INCR4   DMA_SxCR_PBURST_0

 #define STM32_DMA_CR_PBURST_INCR8   DMA_SxCR_PBURST_1

 #define STM32_DMA_CR_PBURST_INCR16  (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)

-#define STM32_DMA_CR_MBURST_MASK    DMA_SxCR_MBURST

+#define STM32_DMA_CR_MBURST_MASK    DMA_SxCR_MBURST_Msk

 #define STM32_DMA_CR_MBURST_SINGLE  0

 #define STM32_DMA_CR_MBURST_INCR4   DMA_SxCR_MBURST_0

 #define STM32_DMA_CR_MBURST_INCR8   DMA_SxCR_MBURST_1

 #define STM32_DMA_CR_MBURST_INCR16  (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)

-#define STM32_DMA_CR_CHSEL_MASK     DMA_SxCR_CHSEL

-#define STM32_DMA_CR_CHSEL(n)       ((n) << 25U)

 /** @} */

 

 /**

- * @name    FCR register constants only found in STM32F2xx/STM32F4xx

+ * @name    FCR register constants

  * @{

  */

 #define STM32_DMA_FCR_RESET_VALUE   0x00000021U

-#define STM32_DMA_FCR_FEIE          DMA_SxFCR_FEIE

-#define STM32_DMA_FCR_FS_MASK       DMA_SxFCR_FS

-#define STM32_DMA_FCR_DMDIS         DMA_SxFCR_DMDIS

-#define STM32_DMA_FCR_FTH_MASK      DMA_SxFCR_FTH

+#define STM32_DMA_FCR_FTH_MASK      DMA_SxFCR_FTH_Msk

 #define STM32_DMA_FCR_FTH_1Q        0

 #define STM32_DMA_FCR_FTH_HALF      DMA_SxFCR_FTH_0

 #define STM32_DMA_FCR_FTH_3Q        DMA_SxFCR_FTH_1

 #define STM32_DMA_FCR_FTH_FULL      (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1)

+#define STM32_DMA_FCR_DMDIS         DMA_SxFCR_DMDIS

+#define STM32_DMA_FCR_FEIE          DMA_SxFCR_FEIE

+#define STM32_DMA_FCR_FS_MASK       DMA_SxFCR_FS_Msk

 /** @} */

 

 /**

diff --git a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
index 14311260d..7d4127a39 100644
--- a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
+++ b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.c
@@ -30,54 +30,6 @@
 /* Driver local definitions.                                                 */

 /*===========================================================================*/

 

-#define SPI1_RX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_RX_DMA_STREAM,                        \

-                       STM32_SPI1_RX_DMA_CHN)

-

-#define SPI1_TX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI1_TX_DMA_STREAM,                        \

-                       STM32_SPI1_TX_DMA_CHN)

-

-#define SPI2_RX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_RX_DMA_STREAM,                        \

-                       STM32_SPI2_RX_DMA_CHN)

-

-#define SPI2_TX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI2_TX_DMA_STREAM,                        \

-                       STM32_SPI2_TX_DMA_CHN)

-

-#define SPI3_RX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_RX_DMA_STREAM,                        \

-                       STM32_SPI3_RX_DMA_CHN)

-

-#define SPI3_TX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI3_TX_DMA_STREAM,                        \

-                       STM32_SPI3_TX_DMA_CHN)

-

-#define SPI4_RX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_RX_DMA_STREAM,                        \

-                       STM32_SPI4_RX_DMA_CHN)

-

-#define SPI4_TX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI4_TX_DMA_STREAM,                        \

-                       STM32_SPI4_TX_DMA_CHN)

-

-#define SPI5_RX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_RX_DMA_STREAM,                        \

-                       STM32_SPI5_RX_DMA_CHN)

-

-#define SPI5_TX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI5_TX_DMA_STREAM,                        \

-                       STM32_SPI5_TX_DMA_CHN)

-

-#define SPI6_RX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_RX_DMA_STREAM,                        \

-                       STM32_SPI6_RX_DMA_CHN)

-

-#define SPI6_TX_DMA_CHANNEL                                                 \

-  STM32_DMA_GETCHANNEL(STM32_SPI_SPI6_TX_DMA_STREAM,                        \

-                       STM32_SPI6_TX_DMA_CHN)

-

 /*===========================================================================*/

 /* Driver exported variables.                                                */

 /*===========================================================================*/

@@ -187,16 +139,14 @@ void spi_lld_init(void) {
 #if STM32_SPI_USE_SPI1

   spiObjectInit(&SPID1);

   SPID1.spi       = SPI1;

-  SPID1.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_STREAM);

-  SPID1.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_STREAM);

-  SPID1.rxdmamode = STM32_DMA_CR_CHSEL(SPI1_RX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |

+  SPID1.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI1_RX_DMA_CHANNEL);

+  SPID1.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI1_TX_DMA_CHANNEL);

+  SPID1.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_P2M |

                     STM32_DMA_CR_TCIE |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

-  SPID1.txdmamode = STM32_DMA_CR_CHSEL(SPI1_TX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |

+  SPID1.txdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI1_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_M2P |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

@@ -205,16 +155,14 @@ void spi_lld_init(void) {
 #if STM32_SPI_USE_SPI2

   spiObjectInit(&SPID2);

   SPID2.spi       = SPI2;

-  SPID2.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_STREAM);

-  SPID2.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_STREAM);

-  SPID2.rxdmamode = STM32_DMA_CR_CHSEL(SPI2_RX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |

+  SPID2.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI2_RX_DMA_CHANNEL);

+  SPID2.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI2_TX_DMA_CHANNEL);

+  SPID2.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_P2M |

                     STM32_DMA_CR_TCIE |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

-  SPID2.txdmamode = STM32_DMA_CR_CHSEL(SPI2_TX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |

+  SPID2.txdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI2_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_M2P |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

@@ -223,16 +171,14 @@ void spi_lld_init(void) {
 #if STM32_SPI_USE_SPI3

   spiObjectInit(&SPID3);

   SPID3.spi       = SPI3;

-  SPID3.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_STREAM);

-  SPID3.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_STREAM);

-  SPID3.rxdmamode = STM32_DMA_CR_CHSEL(SPI3_RX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |

+  SPID3.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI3_RX_DMA_CHANNEL);

+  SPID3.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI3_TX_DMA_CHANNEL);

+  SPID3.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_P2M |

                     STM32_DMA_CR_TCIE |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

-  SPID3.txdmamode = STM32_DMA_CR_CHSEL(SPI3_TX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |

+  SPID3.txdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI3_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_M2P |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

@@ -241,16 +187,14 @@ void spi_lld_init(void) {
 #if STM32_SPI_USE_SPI4

   spiObjectInit(&SPID4);

   SPID4.spi       = SPI4;

-  SPID4.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_STREAM);

-  SPID4.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_STREAM);

-  SPID4.rxdmamode = STM32_DMA_CR_CHSEL(SPI4_RX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |

+  SPID4.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI4_RX_DMA_CHANNEL);

+  SPID4.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI4_TX_DMA_CHANNEL);

+  SPID4.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_P2M |

                     STM32_DMA_CR_TCIE |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

-  SPID4.txdmamode = STM32_DMA_CR_CHSEL(SPI4_TX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |

+  SPID4.txdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI4_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_M2P |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

@@ -259,16 +203,14 @@ void spi_lld_init(void) {
 #if STM32_SPI_USE_SPI5

   spiObjectInit(&SPID5);

   SPID5.spi       = SPI5;

-  SPID5.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM);

-  SPID5.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM);

-  SPID5.rxdmamode = STM32_DMA_CR_CHSEL(SPI5_RX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |

+  SPID5.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_CHANNEL);

+  SPID5.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_CHANNEL);

+  SPID5.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_P2M |

                     STM32_DMA_CR_TCIE |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

-  SPID5.txdmamode = STM32_DMA_CR_CHSEL(SPI5_TX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |

+  SPID5.txdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI5_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_M2P |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

@@ -277,16 +219,14 @@ void spi_lld_init(void) {
 #if STM32_SPI_USE_SPI6

   spiObjectInit(&SPID6);

   SPID6.spi       = SPI6;

-  SPID6.dmarx     = STM32_DMA_STREAM(STM32_SPI_SPI6_RX_DMA_STREAM);

-  SPID6.dmatx     = STM32_DMA_STREAM(STM32_SPI_SPI6_TX_DMA_STREAM);

-  SPID6.rxdmamode = STM32_DMA_CR_CHSEL(SPI6_RX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |

+  SPID6.dmarx     = STM32_BDMA_STREAM(STM32_SPI_SPI6_RX_BDMA_CHANNEL);

+  SPID6.dmatx     = STM32_BDMA_STREAM(STM32_SPI_SPI6_TX_BDMA_CHANNEL);

+  SPID6.rxdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_P2M |

                     STM32_DMA_CR_TCIE |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

-  SPID6.txdmamode = STM32_DMA_CR_CHSEL(SPI6_TX_DMA_CHANNEL) |

-                    STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |

+  SPID6.txdmamode = STM32_DMA_CR_PL(STM32_SPI_SPI6_DMA_PRIORITY) |

                     STM32_DMA_CR_DIR_M2P |

                     STM32_DMA_CR_DMEIE |

                     STM32_DMA_CR_TEIE;

@@ -301,7 +241,7 @@ void spi_lld_init(void) {
  * @notapi

  */

 void spi_lld_start(SPIDriver *spip) {

-  uint32_t ds;

+  uint32_t dsize;

 

   /* If in stopped state then enables the SPI and DMA clocks.*/

   if (spip->state == SPI_STOP) {

@@ -402,37 +342,44 @@ void spi_lld_start(SPIDriver *spip) {
     }

 #endif

 

-#if 0

     /* DMA setup.*/

-    dmaStreamSetPeripheral(spip->dmarx, &spip->spi->DR);

-    dmaStreamSetPeripheral(spip->dmatx, &spip->spi->DR);

-#endif

+    dmaStreamSetPeripheral(spip->dmarx, &spip->spi->RXDR);

+    dmaStreamSetPeripheral(spip->dmatx, &spip->spi->TXDR);

  }

 

-#if 0

   /* Configuration-specific DMA setup.*/

-  ds = spip->config->cr2 & SPI_CR2_DS;

-  if (!ds || (ds <= (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0))) {

-    /* Frame width is 8 bits or smaller.*/

+  dsize = (spip->config->cfg2 & SPI_CFG1_DSIZE_Msk) + 1U;

+  if (dsize <= 8U) {

+    /* Frame width is between 4 and 8 bits.*/

     spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |

                       STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;

     spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |

                       STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE;

   }

-  else {

-    /* Frame width is larger than 8 bits.*/

+  else if (dsize <= 16U) {

+    /* Frame width is between 9 and 16 bits.*/

     spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |

                       STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;

     spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |

                       STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;

   }

+  else {

+    /* Frame width is between 16 and 32 bits.*/

+    spip->rxdmamode = (spip->rxdmamode & ~STM32_DMA_CR_SIZE_MASK) |

+                      STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;

+    spip->txdmamode = (spip->txdmamode & ~STM32_DMA_CR_SIZE_MASK) |

+                      STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD;

+  }

 

   /* SPI setup and enable.*/

   spip->spi->CR1 &= ~SPI_CR1_SPE;

-  spip->spi->CR1  = spip->config->cr1 | SPI_CR1_MSTR;

-  spip->spi->CR2  = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE |

-                    SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;

-#endif

+  spip->spi->CR1  = 0U;

+  spip->spi->CR2  = 0U;

+  spip->spi->CFG1 = spip->config->cfg1 | SPI_CFG1_RXDMAEN | SPI_CFG1_TXDMAEN;

+  spip->spi->CFG2 = spip->config->cfg2 | SPI_CFG2_MASTER;

+//  spip->spi->CFG1 = spip->config->cfg1 | SPI_CR1_MSTR;

+//  spip->spi->CFG2 = spip->config->cfg2 | SPI_CR2_FRXTH | SPI_CR2_SSOE |

+//                    SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;

   spip->spi->CR1 |= SPI_CR1_SPE;

 }

 

@@ -648,19 +595,21 @@ uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
   if ((spip->config->cr2 & SPI_CR2_DS) <= (SPI_CR2_DS_2 |

                                            SPI_CR2_DS_1 |

                                            SPI_CR2_DS_0)) {

-    volatile uint8_t *spidr = (volatile uint8_t *)&spip->spi->DR;

+    volatile uint8_t *spidr = (volatile uint8_t *)&spip->spi->RXDR;

     *spidr = (uint8_t)frame;

     while ((spip->spi->SR & SPI_SR_RXNE) == 0)

       ;

     return (uint16_t)*spidr;

   }

   else {

-    spip->spi->DR = frame;

+    spip->spi->TXDR = frame;

     while ((spip->spi->SR & SPI_SR_RXNE) == 0)

       ;

     return spip->spi->DR;

   }

 #else

+  (void)spip;

+  (void)frame;

   return 0;

 #endif

 }

diff --git a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h
index 99587c8fe..a13e27ff3 100644
--- a/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h
+++ b/os/hal/ports/STM32/LLD/SPIv3/hal_spi_lld.h
@@ -296,102 +296,6 @@
 #error "Invalid DMA priority assigned to SPI6"

 #endif

 

-/* The following checks are only required when there is a DMA able to

-   reassign streams to different channels.*/

-#if STM32_ADVANCED_DMA

-/* Check on the presence of the DMA streams settings in mcuconf.h.*/

-#if STM32_SPI_USE_SPI1 && (!defined(STM32_SPI_SPI1_RX_DMA_STREAM) ||        \

-                           !defined(STM32_SPI_SPI1_TX_DMA_STREAM))

-#error "SPI1 DMA streams not defined"

-#endif

-

-#if STM32_SPI_USE_SPI2 && (!defined(STM32_SPI_SPI2_RX_DMA_STREAM) ||        \

-                           !defined(STM32_SPI_SPI2_TX_DMA_STREAM))

-#error "SPI2 DMA streams not defined"

-#endif

-

-#if STM32_SPI_USE_SPI3 && (!defined(STM32_SPI_SPI3_RX_DMA_STREAM) ||        \

-                           !defined(STM32_SPI_SPI3_TX_DMA_STREAM))

-#error "SPI3 DMA streams not defined"

-#endif

-

-#if STM32_SPI_USE_SPI4 && (!defined(STM32_SPI_SPI4_RX_DMA_STREAM) ||        \

-                           !defined(STM32_SPI_SPI4_TX_DMA_STREAM))

-#error "SPI4 DMA streams not defined"

-#endif

-

-#if STM32_SPI_USE_SPI5 && (!defined(STM32_SPI_SPI5_RX_DMA_STREAM) ||        \

-                           !defined(STM32_SPI_SPI5_TX_DMA_STREAM))

-#error "SPI5 DMA streams not defined"

-#endif

-

-#if STM32_SPI_USE_SPI6 && (!defined(STM32_SPI_SPI6_RX_DMA_STREAM) ||        \

-                           !defined(STM32_SPI_SPI6_TX_DMA_STREAM))

-#error "SPI6 DMA streams not defined"

-#endif

-

-/* Check on the validity of the assigned DMA channels.*/

-#if STM32_SPI_USE_SPI1 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK)

-#error "invalid DMA stream associated to SPI1 RX"

-#endif

-

-#if STM32_SPI_USE_SPI1 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK)

-#error "invalid DMA stream associated to SPI1 TX"

-#endif

-

-#if STM32_SPI_USE_SPI2 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)

-#error "invalid DMA stream associated to SPI2 RX"

-#endif

-

-#if STM32_SPI_USE_SPI2 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)

-#error "invalid DMA stream associated to SPI2 TX"

-#endif

-

-#if STM32_SPI_USE_SPI3 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)

-#error "invalid DMA stream associated to SPI3 RX"

-#endif

-

-#if STM32_SPI_USE_SPI3 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)

-#error "invalid DMA stream associated to SPI3 TX"

-#endif

-

-#if STM32_SPI_USE_SPI4 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_RX_DMA_STREAM, STM32_SPI4_RX_DMA_MSK)

-#error "invalid DMA stream associated to SPI4 RX"

-#endif

-

-#if STM32_SPI_USE_SPI4 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI4_TX_DMA_STREAM, STM32_SPI4_TX_DMA_MSK)

-#error "invalid DMA stream associated to SPI4 TX"

-#endif

-

-#if STM32_SPI_USE_SPI5 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_RX_DMA_STREAM, STM32_SPI5_RX_DMA_MSK)

-#error "invalid DMA stream associated to SPI5 RX"

-#endif

-

-#if STM32_SPI_USE_SPI5 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI5_TX_DMA_STREAM, STM32_SPI5_TX_DMA_MSK)

-#error "invalid DMA stream associated to SPI5 TX"

-#endif

-

-#if STM32_SPI_USE_SPI6 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_RX_DMA_STREAM, STM32_SPI6_RX_DMA_MSK)

-#error "invalid DMA stream associated to SPI6 RX"

-#endif

-

-#if STM32_SPI_USE_SPI6 &&                                                   \

-    !STM32_DMA_IS_VALID_ID(STM32_SPI_SPI6_TX_DMA_STREAM, STM32_SPI6_TX_DMA_MSK)

-#error "invalid DMA stream associated to SPI6 TX"

-#endif

-#endif /* STM32_ADVANCED_DMA */

-

 #if !defined(STM32_DMA_REQUIRED)

 #define STM32_DMA_REQUIRED

 #endif

@@ -453,13 +357,13 @@ typedef struct {
 #endif

   /* End of the mandatory fields.*/

   /**

-   * @brief SPI CR1 register initialization data.

+   * @brief SPI CFG1 register initialization data.

    */

-  uint16_t                  cr1;

+  uint16_t                  cfg1;

   /**

-   * @brief SPI CR2 register initialization data.

+   * @brief SPI CFG2 register initialization data.

    */

-  uint16_t                  cr2;

+  uint16_t                  cfg2;

 } SPIConfig;

 

 /**

diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
index f0c59f905..259272160 100644
--- a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h
@@ -1315,7 +1315,7 @@
  *

  * @api

  */

-#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)

+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)

 

 /**

  * @brief   Disables the TIM16 peripheral clock.

diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h
index bf38828e5..3ef719b3c 100644
--- a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h
@@ -68,7 +68,6 @@
 #define STM32_HAS_DAC2_CH2                  FALSE

 

 /* DMA attributes.*/

-#define STM32_ADVANCED_DMA                  TRUE

 #define STM32_DMA_CACHE_HANDLING            TRUE

 

 #define STM32_HAS_DMA1                      TRUE