Frequencies are right finally.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11185 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 25 insertions, 19 deletions

diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
index 691ffb1b4..fb0cccdac 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
@@ -33,9 +33,9 @@
 #if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING

 

 #if (OSAL_ST_RESOLUTION == 32)

-#define ST_ARR_INIT                         0xFFFFFFFF

+#define ST_ARR_INIT                         0xFFFFFFFFU

 #else

-#define ST_ARR_INIT                         0x0000FFFF

+#define ST_ARR_INIT                         0x0000FFFFU

 #endif

 

 #if STM32_ST_USE_TIMER == 2

@@ -180,11 +180,17 @@
 

 #if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC

 

-#if STM32_HCLK % OSAL_ST_FREQUENCY != 0

+#if defined(STM32_CORE_CK)

+#define SYSTICK_CK                          STM32_CORE_CK

+#else

+#define SYSTICK_CK                          STM32_HCLK

+#endif

+

+#if SYSTICK_CK % OSAL_ST_FREQUENCY != 0

 #error "the selected ST frequency is not obtainable because integer rounding"

 #endif

 

-#if (STM32_HCLK / OSAL_ST_FREQUENCY) - 1 > 0xFFFFFF

+#if (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1 > 0xFFFFFF

 #error "the selected ST frequency is not obtainable because SysTick timer counter limits"

 #endif

 

@@ -292,7 +298,7 @@ void st_lld_init(void) {
 #if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC

   /* Periodic systick mode, the Cortex-Mx internal systick timer is used

      in this mode.*/

-  SysTick->LOAD = (STM32_HCLK / OSAL_ST_FREQUENCY) - 1;

+  SysTick->LOAD = (SYSTICK_CK / OSAL_ST_FREQUENCY) - 1;

   SysTick->VAL = 0;

   SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |

                   SysTick_CTRL_ENABLE_Msk |

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
index 526f1fda1..e1f93a6ff 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
@@ -36,7 +36,7 @@
  * @brief   CMSIS system core clock variable.

  * @note    It is declared in system_stm32f7xx.h.

  */

-uint32_t SystemCoreClock = STM32_C_CK;

+uint32_t SystemCoreClock = STM32_CORE_CK;

 

 /*===========================================================================*/

 /* Driver local variables and types.                                         */

@@ -183,18 +183,23 @@ void stm32_clock_init(void) {
     ;                                       /* Wait until HSI is stable.    */

 

   /* HSI is selected as new source without touching the other fields in

-     CFGR. Clearing the register has to be postponed after HSI is the

-     new source.*/

-  RCC->CFGR &= ~RCC_CFGR_SW;                /* Reset SW to HSI.             */

+     CFGR. This is only required when using a debugger than can cause

+     restarts.*/

+  RCC->CFGR    = 0x00000000U;               /* Reset SW to HSI.             */

   while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)

     ;                                       /* Wait until HSI is selected.  */

 

   /* Registers cleared to reset values.*/

   RCC->CR      = RCC_CR_HSION;             /* CR Reset value.              */

-  RCC->ICSCR   = 0x40000000;               /* ICSCR Reset value.           */

-  RCC->CFGR    = 0x00000000;               /* CFGR reset value.            */

-  RCC->CSR     = 0x00000000;               /* CSR reset value.             */

-  RCC->PLLCFGR = 0x01FF0000;               /* PLLCFGR reset value.         */

+  RCC->ICSCR   = 0x40000000U;              /* ICSCR Reset value.           */

+  RCC->CSR     = 0x00000000U;              /* CSR reset value.             */

+  RCC->PLLCFGR = 0x01FF0000U;              /* PLLCFGR reset value.         */

+

+  /* Other clock-related settings, done before other things because

+     recommended in the RM.*/

+  RCC->CFGR = STM32_MCO2SEL | RCC_CFGR_MCO2PRE_VALUE(STM32_MCO2PRE_VALUE) |

+              STM32_MCO1SEL | RCC_CFGR_MCO1PRE_VALUE(STM32_MCO1PRE_VALUE) |

+              RCC_CFGR_RTCPRE_VALUE(STM32_RTCPRE_VALUE);

 

   /* HSE activation with optional bypass.*/

 #if STM32_HSE_ENABLED == TRUE

@@ -328,11 +333,6 @@ void stm32_clock_init(void) {
     ;

 #endif

 

-  /* Other clock-related settings.*/

-  RCC->CFGR = STM32_MCO2SEL | RCC_CFGR_MCO2PRE_VALUE(STM32_MCO2PRE_VALUE) |

-              STM32_MCO1SEL | RCC_CFGR_MCO1PRE_VALUE(STM32_MCO1PRE_VALUE) |

-              RCC_CFGR_RTCPRE_VALUE(STM32_RTCPRE_VALUE);

-

 #if 0

   /* Peripheral clock sources.*/

   RCC->DCKCFGR2 = STM32_SDMMCSEL  | STM32_CK48MSEL  | STM32_CECSEL    |

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
index 8b530d12e..642bee1d3 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
@@ -2068,7 +2068,7 @@
 /**

  * @brief   Core clock.

  */

-#define STM32_C_CK                  STM32_SYS_D1CPRE_CK

+#define STM32_CORE_CK               STM32_SYS_D1CPRE_CK

 

 /**

  * @brief   HCLK clock.