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| author | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2016-05-26 11:00:08 +0000 |
|---|---|---|
| committer | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2016-05-26 11:00:08 +0000 |
| commit | e9e97281a12b6e1e5afff6ca6e51ab4531ddceb4 (patch) | |
| tree | 2de2eaeb3a18d3c4df4b78e46704075f24fc719f /os/hal/ports | |
| parent | 96f3718cc7e228e4b365cb2cba3d15f6451a8e19 (diff) | |
| download | ChibiOS-e9e97281a12b6e1e5afff6ca6e51ab4531ddceb4.tar.gz ChibiOS-e9e97281a12b6e1e5afff6ca6e51ab4531ddceb4.tar.bz2 ChibiOS-e9e97281a12b6e1e5afff6ca6e51ab4531ddceb4.zip | |
Fixed Bug #745
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9526 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/hal_lld.h | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index 9387336bb..5e4f7e55b 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -433,19 +433,6 @@ /** @} */
/**
- * @name RCC_PLLSAICFGR register bits definitions
- * @{
- */
-#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
-#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
-#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
-#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
-
-#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
-#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
-/** @} */
-
-/**
* @name RCC_BDCR register bits definitions
* @{
*/
@@ -1353,21 +1340,10 @@ #error "invalid STM32_PLLI2SR_VALUE value specified"
#endif
-/*
- * PLLSAI enable check.
- */
-#if !defined(STM32_SAISRC)
-#define STM32_SAISRC STM32_SAISRC_NOCLOCK
-#endif
-
/**
* @brief PLLSAI activation flag.
*/
-#if (STM32_SAISRC == STM32_SAISRC_PLL) || defined(__DOXYGEN__)
-#define STM32_ACTIVATE_PLLSAI TRUE
-#else
#define STM32_ACTIVATE_PLLSAI FALSE
-#endif
/**
* @brief STM32_PLLSAIN field.
|