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authorGiovanni Di Sirio <gdisirio@gmail.com>2018-12-29 17:18:43 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2018-12-29 17:18:43 +0000
commitd9a9844f8e43b725f3bbe53f1d97e6435065adcc (patch)
tree02b59fffce87ea2ab4a2fb7c4fce1526daddc0bb /os/hal/ports
parente3aa427548a678db8b359e24aade7227792b43ad (diff)
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Template fixes.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12491 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports')
-rw-r--r--os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h7
1 files changed, 1 insertions, 6 deletions
diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
index 341fb7687..2417533f9 100644
--- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
+++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.h
@@ -710,12 +710,7 @@ typedef enum {
specified in continuous mode or if the buffer depth is \
greater than one.*/ \
uint32_t cfgr; \
- /* ADC CFGR2 register initialization data. \
- NOTE: The bits DMAEN and DMACFG are enforced internally \
- to the driver, keep them to zero. \
- NOTE: The bits @p ADC_CFGR_CONT or @p ADC_CFGR_DISCEN must be \
- specified in continuous mode or if the buffer depth is \
- greater than one.*/ \
+ /* ADC CFGR2 register initialization data.*/ \
uint32_t cfgr2; \
/* ADC TR1 register initialization data.*/ \
uint32_t tr1; \