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authorGiovanni Di Sirio <gdisirio@gmail.com>2018-07-07 09:29:36 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2018-07-07 09:29:36 +0000
commitd8c1554717a8162fe2741533a50631f7ae99d067 (patch)
treed94b88bfe988c395972a079eeef9688b7216df7e /os/hal/ports
parentab1217b961ffe22e96b10e6c935850bef328f9c2 (diff)
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Fixed a regression on F2 devices.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12137 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports')
-rw-r--r--os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
index 87d60a8ed..2f2146416 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
@@ -1475,6 +1475,7 @@
#error "invalid STM32_PLLQ_VALUE value specified"
#endif
+#if defined(STM32F4XX) || defined(__DOXYGEN__)
/**
* @brief STM32_PLLR field.
*/
@@ -1484,6 +1485,9 @@
#else
#error "invalid STM32_PLLR_VALUE value specified"
#endif
+#else /* !defined(STM32F4XX) */
+#define STM32_PLLR 0
+#endif /* !defined(STM32F4XX) */
/**
* @brief PLL VCO frequency.