diff options
| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-05 13:44:33 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-05 13:44:33 +0000 |
| commit | c07fd3935f473c3627b970c6be0cc4583705f664 (patch) | |
| tree | 65f3ab30eb0bd4c2be3a7ff90c8b2f48b81ddbbe /os/hal/ports | |
| parent | 9be84e95da4f77d76969149b5629e72cdfc55581 (diff) | |
| download | ChibiOS-c07fd3935f473c3627b970c6be0cc4583705f664.tar.gz ChibiOS-c07fd3935f473c3627b970c6be0cc4583705f664.tar.bz2 ChibiOS-c07fd3935f473c3627b970c6be0cc4583705f664.zip | |
STM32F4xx now uses DMAv2 and ADCv2 shared drivers.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8161 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/adc_lld.c | 427 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/adc_lld.h | 563 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/platform.mk | 10 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_dma.c | 527 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_dma.h | 461 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 148 |
6 files changed, 154 insertions, 1982 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/adc_lld.c b/os/hal/ports/STM32/STM32F4xx/adc_lld.c deleted file mode 100644 index 65556b1a3..000000000 --- a/os/hal/ports/STM32/STM32F4xx/adc_lld.c +++ /dev/null @@ -1,427 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F4xx/adc_lld.c
- * @brief STM32F4xx/STM32F2xx ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-#define ADC1_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_CHN)
-
-#define ADC2_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_CHN)
-
-#define ADC3_DMA_CHANNEL \
- STM32_DMA_GETCHANNEL(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_CHN)
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/** @brief ADC2 driver identifier.*/
-#if STM32_ADC_USE_ADC2 || defined(__DOXYGEN__)
-ADCDriver ADCD2;
-#endif
-
-/** @brief ADC3 driver identifier.*/
-#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
-ADCDriver ADCD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/**
- * @brief ADC DMA ISR service routine.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- * @param[in] flags pre-shifted content of the ISR register
- */
-static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
-
- /* DMA errors handling.*/
- if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
- /* DMA, this could help only if the DMA tries to access an unmapped
- address space or violates alignment rules.*/
- _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
- }
- else {
- /* It is possible that the conversion group has already be reset by the
- ADC error handler, in this case this interrupt is spurious.*/
- if (adcp->grpp != NULL) {
- if ((flags & STM32_DMA_ISR_TCIF) != 0) {
- /* Transfer complete processing.*/
- _adc_isr_full_code(adcp);
- }
- else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
- /* Half transfer processing.*/
- _adc_isr_half_code(adcp);
- }
- }
- }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 || STM32_ADC_USE_ADC2 || STM32_ADC_USE_ADC3 || \
- defined(__DOXYGEN__)
-/**
- * @brief ADC interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector88) {
- uint32_t sr;
-
- OSAL_IRQ_PROLOGUE();
-
-#if STM32_ADC_USE_ADC1
- sr = ADC1->SR;
- ADC1->SR = 0;
- /* Note, an overflow may occur after the conversion ended before the driver
- is able to stop the ADC, this is why the DMA channel is checked too.*/
- if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
- /* ADC overflow condition, this could happen only if the DMA is unable
- to read data fast enough.*/
- if (ADCD1.grpp != NULL)
- _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
- }
- /* TODO: Add here analog watchdog handling.*/
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC2
- sr = ADC2->SR;
- ADC2->SR = 0;
- /* Note, an overflow may occur after the conversion ended before the driver
- is able to stop the ADC, this is why the DMA channel is checked too.*/
- if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD2.dmastp) > 0)) {
- /* ADC overflow condition, this could happen only if the DMA is unable
- to read data fast enough.*/
- if (ADCD2.grpp != NULL)
- _adc_isr_error_code(&ADCD2, ADC_ERR_OVERFLOW);
- }
- /* TODO: Add here analog watchdog handling.*/
-#endif /* STM32_ADC_USE_ADC2 */
-
-#if STM32_ADC_USE_ADC3
- sr = ADC3->SR;
- ADC3->SR = 0;
- /* Note, an overflow may occur after the conversion ended before the driver
- is able to stop the ADC, this is why the DMA channel is checked too.*/
- if ((sr & ADC_SR_OVR) && (dmaStreamGetTransactionSize(ADCD3.dmastp) > 0)) {
- /* ADC overflow condition, this could happen only if the DMA is unable
- to read data fast enough.*/
- if (ADCD3.grpp != NULL)
- _adc_isr_error_code(&ADCD3, ADC_ERR_OVERFLOW);
- }
- /* TODO: Add here analog watchdog handling.*/
-#endif /* STM32_ADC_USE_ADC3 */
-
- OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if STM32_ADC_USE_ADC1
- /* Driver initialization.*/
- adcObjectInit(&ADCD1);
- ADCD1.adc = ADC1;
- ADCD1.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC1_DMA_STREAM);
- ADCD1.dmamode = STM32_DMA_CR_CHSEL(ADC1_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |
- STM32_DMA_CR_DIR_P2M |
- STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
- STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_ADC_USE_ADC2
- /* Driver initialization.*/
- adcObjectInit(&ADCD2);
- ADCD2.adc = ADC2;
- ADCD2.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC2_DMA_STREAM);
- ADCD2.dmamode = STM32_DMA_CR_CHSEL(ADC2_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_ADC_ADC2_DMA_PRIORITY) |
- STM32_DMA_CR_DIR_P2M |
- STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
- STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-#endif
-
-#if STM32_ADC_USE_ADC3
- /* Driver initialization.*/
- adcObjectInit(&ADCD3);
- ADCD3.adc = ADC3;
- ADCD3.dmastp = STM32_DMA_STREAM(STM32_ADC_ADC3_DMA_STREAM);
- ADCD3.dmamode = STM32_DMA_CR_CHSEL(ADC3_DMA_CHANNEL) |
- STM32_DMA_CR_PL(STM32_ADC_ADC3_DMA_PRIORITY) |
- STM32_DMA_CR_DIR_P2M |
- STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |
- STM32_DMA_CR_MINC | STM32_DMA_CR_TCIE |
- STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
-#endif
-
- /* The shared vector is initialized on driver initialization and never
- disabled.*/
- nvicEnableVector(ADC_IRQn, STM32_ADC_IRQ_PRIORITY);
-}
-
-/**
- * @brief Configures and activates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
- /* If in stopped state then enables the ADC and DMA clocks.*/
- if (adcp->state == ADC_STOP) {
-#if STM32_ADC_USE_ADC1
- if (&ADCD1 == adcp) {
- bool b;
- b = dmaStreamAllocate(adcp->dmastp,
- STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
- (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
- (void *)adcp);
- osalDbgAssert(!b, "stream already allocated");
- dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
- rccEnableADC1(FALSE);
- }
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC2
- if (&ADCD2 == adcp) {
- bool b;
- b = dmaStreamAllocate(adcp->dmastp,
- STM32_ADC_ADC2_DMA_IRQ_PRIORITY,
- (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
- (void *)adcp);
- osalDbgAssert(!b, "stream already allocated");
- dmaStreamSetPeripheral(adcp->dmastp, &ADC2->DR);
- rccEnableADC2(FALSE);
- }
-#endif /* STM32_ADC_USE_ADC2 */
-
-#if STM32_ADC_USE_ADC3
- if (&ADCD3 == adcp) {
- bool b;
- b = dmaStreamAllocate(adcp->dmastp,
- STM32_ADC_ADC3_DMA_IRQ_PRIORITY,
- (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
- (void *)adcp);
- osalDbgAssert(!b, "stream already allocated");
- dmaStreamSetPeripheral(adcp->dmastp, &ADC3->DR);
- rccEnableADC3(FALSE);
- }
-#endif /* STM32_ADC_USE_ADC3 */
-
- /* This is a common register but apparently it requires that at least one
- of the ADCs is clocked in order to allow writing, see bug 3575297.*/
- ADC->CCR = (ADC->CCR & (ADC_CCR_TSVREFE | ADC_CCR_VBATE)) |
- (STM32_ADC_ADCPRE << 16);
-
- /* ADC initial setup, starting the analog part here in order to reduce
- the latency when starting a conversion.*/
- adcp->adc->CR1 = 0;
- adcp->adc->CR2 = 0;
- adcp->adc->CR2 = ADC_CR2_ADON;
- }
-}
-
-/**
- * @brief Deactivates the ADC peripheral.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
- /* If in ready state then disables the ADC clock.*/
- if (adcp->state == ADC_READY) {
- dmaStreamRelease(adcp->dmastp);
- adcp->adc->CR1 = 0;
- adcp->adc->CR2 = 0;
-
-#if STM32_ADC_USE_ADC1
- if (&ADCD1 == adcp)
- rccDisableADC1(FALSE);
-#endif
-
-#if STM32_ADC_USE_ADC2
- if (&ADCD2 == adcp)
- rccDisableADC2(FALSE);
-#endif
-
-#if STM32_ADC_USE_ADC3
- if (&ADCD3 == adcp)
- rccDisableADC3(FALSE);
-#endif
- }
-}
-
-/**
- * @brief Starts an ADC conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
- uint32_t mode;
- uint32_t cr2;
- const ADCConversionGroup *grpp = adcp->grpp;
-
- /* DMA setup.*/
- mode = adcp->dmamode;
- if (grpp->circular) {
- mode |= STM32_DMA_CR_CIRC;
- if (adcp->depth > 1) {
- /* If circular buffer depth > 1, then the half transfer interrupt
- is enabled in order to allow streaming processing.*/
- mode |= STM32_DMA_CR_HTIE;
- }
- }
- dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
- dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
- (uint32_t)adcp->depth);
- dmaStreamSetMode(adcp->dmastp, mode);
- dmaStreamEnable(adcp->dmastp);
-
- /* ADC setup.*/
- adcp->adc->SR = 0;
- adcp->adc->SMPR1 = grpp->smpr1;
- adcp->adc->SMPR2 = grpp->smpr2;
- adcp->adc->SQR1 = grpp->sqr1;
- adcp->adc->SQR2 = grpp->sqr2;
- adcp->adc->SQR3 = grpp->sqr3;
-
- /* ADC configuration and start.*/
- adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
-
- /* Enforcing the mandatory bits in CR2.*/
- cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON;
-
- /* The start method is different dependign if HW or SW triggered, the
- start is performed using the method specified in the CR2 configuration.*/
- if ((cr2 & ADC_CR2_SWSTART) != 0) {
- /* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/
- adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART;
-
- /* Finally enabling ADC_CR2_SWSTART.*/
- adcp->adc->CR2 = (cr2 | ADC_CR2_CONT);
- }
- else
- adcp->adc->CR2 = cr2;
-}
-
-/**
- * @brief Stops an ongoing conversion.
- *
- * @param[in] adcp pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
- dmaStreamDisable(adcp->dmastp);
- adcp->adc->CR1 = 0;
- adcp->adc->CR2 = 0;
- adcp->adc->CR2 = ADC_CR2_ADON;
-}
-
-/**
- * @brief Enables the TSVREFE bit.
- * @details The TSVREFE bit is required in order to sample the internal
- * temperature sensor and internal reference voltage.
- * @note This is an STM32-only functionality.
- */
-void adcSTM32EnableTSVREFE(void) {
-
- ADC->CCR |= ADC_CCR_TSVREFE;
-}
-
-/**
- * @brief Disables the TSVREFE bit.
- * @details The TSVREFE bit is required in order to sample the internal
- * temperature sensor and internal reference voltage.
- * @note This is an STM32-only functionality.
- */
-void adcSTM32DisableTSVREFE(void) {
-
- ADC->CCR &= ~ADC_CCR_TSVREFE;
-}
-
-/**
- * @brief Enables the VBATE bit.
- * @details The VBATE bit is required in order to sample the VBAT channel.
- * @note This is an STM32-only functionality.
- * @note This function is meant to be called after @p adcStart().
- */
-void adcSTM32EnableVBATE(void) {
-
- ADC->CCR |= ADC_CCR_VBATE;
-}
-
-/**
- * @brief Disables the VBATE bit.
- * @details The VBATE bit is required in order to sample the VBAT channel.
- * @note This is an STM32-only functionality.
- * @note This function is meant to be called after @p adcStart().
- */
-void adcSTM32DisableVBATE(void) {
-
- ADC->CCR &= ~ADC_CCR_VBATE;
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/adc_lld.h b/os/hal/ports/STM32/STM32F4xx/adc_lld.h deleted file mode 100644 index df8e784b1..000000000 --- a/os/hal/ports/STM32/STM32F4xx/adc_lld.h +++ /dev/null @@ -1,563 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F4xx/adc_lld.h
- * @brief STM32F4xx/STM32F2xx ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @name Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief Minimum ADC clock frequency.
- */
-#define STM32_ADCCLK_MIN 600000
-
-/**
- * @brief Maximum ADC clock frequency.
- */
-#if defined(STM32F4XX) || defined(__DOXYGEN__)
-#define STM32_ADCCLK_MAX 36000000
-#else
-#define STM32_ADCCLK_MAX 30000000
-#endif
-/** @} */
-
-/**
- * @name Triggers selection
- * @{
- */
-#define ADC_CR2_EXTSEL_SRC(n) ((n) << 24) /**< @brief Trigger source. */
-/** @} */
-
-/**
- * @name ADC clock divider settings
- * @{
- */
-#define ADC_CCR_ADCPRE_DIV2 0
-#define ADC_CCR_ADCPRE_DIV4 1
-#define ADC_CCR_ADCPRE_DIV6 2
-#define ADC_CCR_ADCPRE_DIV8 3
-/** @} */
-
-/**
- * @name Available analog channels
- * @{
- */
-#define ADC_CHANNEL_IN0 0 /**< @brief External analog input 0. */
-#define ADC_CHANNEL_IN1 1 /**< @brief External analog input 1. */
-#define ADC_CHANNEL_IN2 2 /**< @brief External analog input 2. */
-#define ADC_CHANNEL_IN3 3 /**< @brief External analog input 3. */
-#define ADC_CHANNEL_IN4 4 /**< @brief External analog input 4. */
-#define ADC_CHANNEL_IN5 5 /**< @brief External analog input 5. */
-#define ADC_CHANNEL_IN6 6 /**< @brief External analog input 6. */
-#define ADC_CHANNEL_IN7 7 /**< @brief External analog input 7. */
-#define ADC_CHANNEL_IN8 8 /**< @brief External analog input 8. */
-#define ADC_CHANNEL_IN9 9 /**< @brief External analog input 9. */
-#define ADC_CHANNEL_IN10 10 /**< @brief External analog input 10. */
-#define ADC_CHANNEL_IN11 11 /**< @brief External analog input 11. */
-#define ADC_CHANNEL_IN12 12 /**< @brief External analog input 12. */
-#define ADC_CHANNEL_IN13 13 /**< @brief External analog input 13. */
-#define ADC_CHANNEL_IN14 14 /**< @brief External analog input 14. */
-#define ADC_CHANNEL_IN15 15 /**< @brief External analog input 15. */
-#define ADC_CHANNEL_SENSOR 16 /**< @brief Internal temperature sensor.
- @note Available onADC1 only. */
-#define ADC_CHANNEL_VREFINT 17 /**< @brief Internal reference.
- @note Available onADC1 only. */
-#define ADC_CHANNEL_VBAT 18 /**< @brief VBAT.
- @note Available onADC1 only. */
-/** @} */
-
-/**
- * @name Sampling rates
- * @{
- */
-#define ADC_SAMPLE_3 0 /**< @brief 3 cycles sampling time. */
-#define ADC_SAMPLE_15 1 /**< @brief 15 cycles sampling time. */
-#define ADC_SAMPLE_28 2 /**< @brief 28 cycles sampling time. */
-#define ADC_SAMPLE_56 3 /**< @brief 56 cycles sampling time. */
-#define ADC_SAMPLE_84 4 /**< @brief 84 cycles sampling time. */
-#define ADC_SAMPLE_112 5 /**< @brief 112 cycles sampling time. */
-#define ADC_SAMPLE_144 6 /**< @brief 144 cycles sampling time. */
-#define ADC_SAMPLE_480 7 /**< @brief 480 cycles sampling time. */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/**
- * @name Configuration options
- * @{
- */
-/**
- * @brief ADC common clock divider.
- * @note This setting is influenced by the VDDA voltage and other
- * external conditions, please refer to the datasheet for more
- * info.<br>
- * See section 5.3.20 "12-bit ADC characteristics".
- */
-#if !defined(STM32_ADC_ADCPRE) || defined(__DOXYGEN__)
-#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV2
-#endif
-
-/**
- * @brief ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC1 FALSE
-#endif
-
-/**
- * @brief ADC2 driver enable switch.
- * @details If set to @p TRUE the support for ADC2 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_ADC_USE_ADC2) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC2 FALSE
-#endif
-
-/**
- * @brief ADC3 driver enable switch.
- * @details If set to @p TRUE the support for ADC3 is included.
- * @note The default is @p TRUE.
- */
-#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC3 FALSE
-#endif
-
-/**
- * @brief DMA stream used for ADC1 operations.
- */
-#if !defined(STM32_ADC_ADC1_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
-#endif
-
-/**
- * @brief DMA stream used for ADC2 operations.
- */
-#if !defined(STM32_ADC_ADC2_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
-#endif
-
-/**
- * @brief DMA stream used for ADC3 operations.
- */
-#if !defined(STM32_ADC_ADC3_DMA_STREAM) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
-#endif
-
-/**
- * @brief ADC1 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief ADC2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC2_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC2_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief ADC3 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC3_DMA_PRIORITY 2
-#endif
-
-/**
- * @brief ADC interrupt priority level setting.
- * @note This setting is shared among ADC1, ADC2 and ADC3 because
- * all ADCs share the same vector.
- */
-#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_IRQ_PRIORITY 5
-#endif
-
-/**
- * @brief ADC1 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
-#endif
-
-/**
- * @brief ADC2 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC2_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
-#endif
-
-/**
- * @brief ADC3 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
-#endif
-
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
-#error "ADC1 not present in the selected device"
-#endif
-
-#if STM32_ADC_USE_ADC2 && !STM32_HAS_ADC2
-#error "ADC2 not present in the selected device"
-#endif
-
-#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
-#error "ADC3 not present in the selected device"
-#endif
-
-#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC2 && !STM32_ADC_USE_ADC3
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-#if STM32_ADC_USE_ADC1 && \
- !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC1_DMA_STREAM, STM32_ADC1_DMA_MSK)
-#error "invalid DMA stream associated to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC2 && \
- !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC2_DMA_STREAM, STM32_ADC2_DMA_MSK)
-#error "invalid DMA stream associated to ADC2"
-#endif
-
-#if STM32_ADC_USE_ADC3 && \
- !STM32_DMA_IS_VALID_ID(STM32_ADC_ADC3_DMA_STREAM, STM32_ADC3_DMA_MSK)
-#error "invalid DMA stream associated to ADC3"
-#endif
-
-/* ADC clock related settings and checks.*/
-#if STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV2
-#define STM32_ADCCLK (STM32_PCLK2 / 2)
-#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV4
-#define STM32_ADCCLK (STM32_PCLK2 / 4)
-#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV6
-#define STM32_ADCCLK (STM32_PCLK2 / 6)
-#elif STM32_ADC_ADCPRE == ADC_CCR_ADCPRE_DIV8
-#define STM32_ADCCLK (STM32_PCLK2 / 8)
-#else
-#error "invalid STM32_ADC_ADCPRE value specified"
-#endif
-
-#if (STM32_ADCCLK < STM32_ADCCLK_MIN) || (STM32_ADCCLK > STM32_ADCCLK_MAX)
-#error "STM32_ADCCLK outside acceptable range (STM32_ADCCLK_MIN...STM32_ADCCLK_MAX)"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief ADC sample data type.
- */
-typedef uint16_t adcsample_t;
-
-/**
- * @brief Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief Possible ADC failure causes.
- * @note Error codes are architecture dependent and should not relied
- * upon.
- */
-typedef enum {
- ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
- ADC_ERR_OVERFLOW = 1 /**< ADC overflow condition. */
-} adcerror_t;
-
-/**
- * @brief Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief ADC notification callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] buffer pointer to the most recent samples data
- * @param[in] n number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief ADC error callback type.
- *
- * @param[in] adcp pointer to the @p ADCDriver object triggering the
- * callback
- * @param[in] err ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- * operation.
- * @note The use of this configuration structure requires knowledge of
- * STM32 ADC cell registers interface, please refer to the STM32
- * reference manual for details.
- */
-typedef struct {
- /**
- * @brief Enables the circular buffer mode for the group.
- */
- bool circular;
- /**
- * @brief Number of the analog channels belonging to the conversion group.
- */
- adc_channels_num_t num_channels;
- /**
- * @brief Callback function associated to the group or @p NULL.
- */
- adccallback_t end_cb;
- /**
- * @brief Error callback or @p NULL.
- */
- adcerrorcallback_t error_cb;
- /* End of the mandatory fields.*/
- /**
- * @brief ADC CR1 register initialization data.
- * @note All the required bits must be defined into this field except
- * @p ADC_CR1_SCAN that is enforced inside the driver.
- */
- uint32_t cr1;
- /**
- * @brief ADC CR2 register initialization data.
- * @note All the required bits must be defined into this field except
- * @p ADC_CR2_DMA, @p ADC_CR2_CONT and @p ADC_CR2_ADON that are
- * enforced inside the driver.
- */
- uint32_t cr2;
- /**
- * @brief ADC SMPR1 register initialization data.
- * @details In this field must be specified the sample times for channels
- * 10...18.
- */
- uint32_t smpr1;
- /**
- * @brief ADC SMPR2 register initialization data.
- * @details In this field must be specified the sample times for channels
- * 0...9.
- */
- uint32_t smpr2;
- /**
- * @brief ADC SQR1 register initialization data.
- * @details Conversion group sequence 13...16 + sequence length.
- */
- uint32_t sqr1;
- /**
- * @brief ADC SQR2 register initialization data.
- * @details Conversion group sequence 7...12.
- */
- uint32_t sqr2;
- /**
- * @brief ADC SQR3 register initialization data.
- * @details Conversion group sequence 1...6.
- */
- uint32_t sqr3;
-} ADCConversionGroup;
-
-/**
- * @brief Driver configuration structure.
- * @note It could be empty on some architectures.
- */
-typedef struct {
- uint32_t dummy;
-} ADCConfig;
-
-/**
- * @brief Structure representing an ADC driver.
- */
-struct ADCDriver {
- /**
- * @brief Driver state.
- */
- adcstate_t state;
- /**
- * @brief Current configuration data.
- */
- const ADCConfig *config;
- /**
- * @brief Current samples buffer pointer or @p NULL.
- */
- adcsample_t *samples;
- /**
- * @brief Current samples buffer depth or @p 0.
- */
- size_t depth;
- /**
- * @brief Current conversion group pointer or @p NULL.
- */
- const ADCConversionGroup *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
- /**
- * @brief Waiting thread.
- */
- thread_reference_t thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
- /**
- * @brief Mutex protecting the peripheral.
- */
- mutex_t mutex;
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
- ADC_DRIVER_EXT_FIELDS
-#endif
- /* End of the mandatory fields.*/
- /**
- * @brief Pointer to the ADCx registers block.
- */
- ADC_TypeDef *adc;
- /**
- * @brief Pointer to associated DMA channel.
- */
- const stm32_dma_stream_t *dmastp;
- /**
- * @brief DMA mode bit mask.
- */
- uint32_t dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name Sequences building helper macros
- * @{
- */
-/**
- * @brief Number of channels in a conversion sequence.
- */
-#define ADC_SQR1_NUM_CH(n) (((n) - 1) << 20)
-
-#define ADC_SQR3_SQ1_N(n) ((n) << 0) /**< @brief 1st channel in seq. */
-#define ADC_SQR3_SQ2_N(n) ((n) << 5) /**< @brief 2nd channel in seq. */
-#define ADC_SQR3_SQ3_N(n) ((n) << 10) /**< @brief 3rd channel in seq. */
-#define ADC_SQR3_SQ4_N(n) ((n) << 15) /**< @brief 4th channel in seq. */
-#define ADC_SQR3_SQ5_N(n) ((n) << 20) /**< @brief 5th channel in seq. */
-#define ADC_SQR3_SQ6_N(n) ((n) << 25) /**< @brief 6th channel in seq. */
-
-#define ADC_SQR2_SQ7_N(n) ((n) << 0) /**< @brief 7th channel in seq. */
-#define ADC_SQR2_SQ8_N(n) ((n) << 5) /**< @brief 8th channel in seq. */
-#define ADC_SQR2_SQ9_N(n) ((n) << 10) /**< @brief 9th channel in seq. */
-#define ADC_SQR2_SQ10_N(n) ((n) << 15) /**< @brief 10th channel in seq.*/
-#define ADC_SQR2_SQ11_N(n) ((n) << 20) /**< @brief 11th channel in seq.*/
-#define ADC_SQR2_SQ12_N(n) ((n) << 25) /**< @brief 12th channel in seq.*/
-
-#define ADC_SQR1_SQ13_N(n) ((n) << 0) /**< @brief 13th channel in seq.*/
-#define ADC_SQR1_SQ14_N(n) ((n) << 5) /**< @brief 14th channel in seq.*/
-#define ADC_SQR1_SQ15_N(n) ((n) << 10) /**< @brief 15th channel in seq.*/
-#define ADC_SQR1_SQ16_N(n) ((n) << 15) /**< @brief 16th channel in seq.*/
-/** @} */
-
-/**
- * @name Sampling rate settings helper macros
- * @{
- */
-#define ADC_SMPR2_SMP_AN0(n) ((n) << 0) /**< @brief AN0 sampling time. */
-#define ADC_SMPR2_SMP_AN1(n) ((n) << 3) /**< @brief AN1 sampling time. */
-#define ADC_SMPR2_SMP_AN2(n) ((n) << 6) /**< @brief AN2 sampling time. */
-#define ADC_SMPR2_SMP_AN3(n) ((n) << 9) /**< @brief AN3 sampling time. */
-#define ADC_SMPR2_SMP_AN4(n) ((n) << 12) /**< @brief AN4 sampling time. */
-#define ADC_SMPR2_SMP_AN5(n) ((n) << 15) /**< @brief AN5 sampling time. */
-#define ADC_SMPR2_SMP_AN6(n) ((n) << 18) /**< @brief AN6 sampling time. */
-#define ADC_SMPR2_SMP_AN7(n) ((n) << 21) /**< @brief AN7 sampling time. */
-#define ADC_SMPR2_SMP_AN8(n) ((n) << 24) /**< @brief AN8 sampling time. */
-#define ADC_SMPR2_SMP_AN9(n) ((n) << 27) /**< @brief AN9 sampling time. */
-
-#define ADC_SMPR1_SMP_AN10(n) ((n) << 0) /**< @brief AN10 sampling time. */
-#define ADC_SMPR1_SMP_AN11(n) ((n) << 3) /**< @brief AN11 sampling time. */
-#define ADC_SMPR1_SMP_AN12(n) ((n) << 6) /**< @brief AN12 sampling time. */
-#define ADC_SMPR1_SMP_AN13(n) ((n) << 9) /**< @brief AN13 sampling time. */
-#define ADC_SMPR1_SMP_AN14(n) ((n) << 12) /**< @brief AN14 sampling time. */
-#define ADC_SMPR1_SMP_AN15(n) ((n) << 15) /**< @brief AN15 sampling time. */
-#define ADC_SMPR1_SMP_SENSOR(n) ((n) << 18) /**< @brief Temperature Sensor
- sampling time. */
-#define ADC_SMPR1_SMP_VREF(n) ((n) << 21) /**< @brief Voltage Reference
- sampling time. */
-#define ADC_SMPR1_SMP_VBAT(n) ((n) << 24) /**< @brief VBAT sampling time. */
-/** @} */
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#if STM32_ADC_USE_ADC2 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD2;
-#endif
-
-#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void adc_lld_init(void);
- void adc_lld_start(ADCDriver *adcp);
- void adc_lld_stop(ADCDriver *adcp);
- void adc_lld_start_conversion(ADCDriver *adcp);
- void adc_lld_stop_conversion(ADCDriver *adcp);
- void adcSTM32EnableTSVREFE(void);
- void adcSTM32DisableTSVREFE(void);
- void adcSTM32EnableVBATE(void);
- void adcSTM32DisableVBATE(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk index f1f9fcd72..1aa017033 100644 --- a/os/hal/ports/STM32/STM32F4xx/platform.mk +++ b/os/hal/ports/STM32/STM32F4xx/platform.mk @@ -3,11 +3,11 @@ ifeq ($(USE_SMART_BUILD),yes) HALCONF := $(strip $(shell cat halconf.h | egrep -e "define"))
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
- $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/stm32_dma.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c
ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)
-PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/adc_lld.c
+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c
endif
ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),)
PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/CANV1/can_lld.c
@@ -60,13 +60,13 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c endif
else
PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \
- $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/stm32_dma.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/hal_lld.c \
- $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/adc_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/ext_lld_isr.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2/adc_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1/i2c_lld.c \
$(CHIBIOS)/os/hal/ports/STM32/LLD/MACv1/mac_lld.c \
@@ -86,8 +86,10 @@ endif # Required include directories
PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
$(CHIBIOS)/os/hal/ports/STM32/STM32F4xx \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv2 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \
+ $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv2 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2 \
$(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv1 \
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_dma.c b/os/hal/ports/STM32/STM32F4xx/stm32_dma.c deleted file mode 100644 index 54ff8c295..000000000 --- a/os/hal/ports/STM32/STM32F4xx/stm32_dma.c +++ /dev/null @@ -1,527 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F4xx/stm32_dma.c
- * @brief Enhanced DMA helper driver code.
- *
- * @addtogroup STM32F4xx_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- * shared resource, this driver allows to allocate and free DMA
- * streams at runtime in order to allow all the other device
- * drivers to coordinate the access to the resource.
- * @note The DMA ISR handlers are all declared into this module because
- * sharing, the various device drivers can associate a callback to
- * ISRs when allocating streams.
- * @{
- */
-
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
- has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions. */
-/*===========================================================================*/
-
-/**
- * @brief Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK 0x000000FF
-
-/**
- * @brief Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK 0x0000FF00
-
-/**
- * @brief Post-reset value of the stream CR register.
- */
-#define STM32_DMA_CR_RESET_VALUE 0x00000000
-
-/**
- * @brief Post-reset value of the stream FCR register.
- */
-#define STM32_DMA_FCR_RESET_VALUE 0x00000021
-
-/*===========================================================================*/
-/* Driver exported variables. */
-/*===========================================================================*/
-
-/**
- * @brief DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- * identifier and the involved physical registers.
- * @note Don't use this array directly, use the appropriate wrapper macros
- * instead: @p STM32_DMA1_STREAM0, @p STM32_DMA1_STREAM1 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
- {DMA1_Stream0, &DMA1->LIFCR, 0, 0, DMA1_Stream0_IRQn},
- {DMA1_Stream1, &DMA1->LIFCR, 6, 1, DMA1_Stream1_IRQn},
- {DMA1_Stream2, &DMA1->LIFCR, 16, 2, DMA1_Stream2_IRQn},
- {DMA1_Stream3, &DMA1->LIFCR, 22, 3, DMA1_Stream3_IRQn},
- {DMA1_Stream4, &DMA1->HIFCR, 0, 4, DMA1_Stream4_IRQn},
- {DMA1_Stream5, &DMA1->HIFCR, 6, 5, DMA1_Stream5_IRQn},
- {DMA1_Stream6, &DMA1->HIFCR, 16, 6, DMA1_Stream6_IRQn},
- {DMA1_Stream7, &DMA1->HIFCR, 22, 7, DMA1_Stream7_IRQn},
- {DMA2_Stream0, &DMA2->LIFCR, 0, 8, DMA2_Stream0_IRQn},
- {DMA2_Stream1, &DMA2->LIFCR, 6, 9, DMA2_Stream1_IRQn},
- {DMA2_Stream2, &DMA2->LIFCR, 16, 10, DMA2_Stream2_IRQn},
- {DMA2_Stream3, &DMA2->LIFCR, 22, 11, DMA2_Stream3_IRQn},
- {DMA2_Stream4, &DMA2->HIFCR, 0, 12, DMA2_Stream4_IRQn},
- {DMA2_Stream5, &DMA2->HIFCR, 6, 13, DMA2_Stream5_IRQn},
- {DMA2_Stream6, &DMA2->HIFCR, 16, 14, DMA2_Stream6_IRQn},
- {DMA2_Stream7, &DMA2->HIFCR, 22, 15, DMA2_Stream7_IRQn},
-};
-
-/*===========================================================================*/
-/* Driver local variables and types. */
-/*===========================================================================*/
-
-/**
- * @brief DMA ISR redirector type.
- */
-typedef struct {
- stm32_dmaisr_t dma_func; /**< @brief DMA callback function. */
- void *dma_param; /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
-/*===========================================================================*/
-/* Driver local functions. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers. */
-/*===========================================================================*/
-
-/**
- * @brief DMA1 stream 0 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector6C) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->LISR >> 0) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 0;
- if (dma_isr_redir[0].dma_func)
- dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector70) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->LISR >> 6) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 6;
- if (dma_isr_redir[1].dma_func)
- dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 2 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector74) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->LISR >> 16) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 16;
- if (dma_isr_redir[2].dma_func)
- dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 3 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector78) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->LISR >> 22) & STM32_DMA_ISR_MASK;
- DMA1->LIFCR = flags << 22;
- if (dma_isr_redir[3].dma_func)
- dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 4 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector7C) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->HISR >> 0) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 0;
- if (dma_isr_redir[4].dma_func)
- dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 5 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector80) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->HISR >> 6) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 6;
- if (dma_isr_redir[5].dma_func)
- dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 6 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector84) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->HISR >> 16) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 16;
- if (dma_isr_redir[6].dma_func)
- dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA1 stream 7 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(VectorFC) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA1->HISR >> 22) & STM32_DMA_ISR_MASK;
- DMA1->HIFCR = flags << 22;
- if (dma_isr_redir[7].dma_func)
- dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 0 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector120) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->LISR >> 0) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 0;
- if (dma_isr_redir[8].dma_func)
- dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 1 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector124) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->LISR >> 6) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 6;
- if (dma_isr_redir[9].dma_func)
- dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 2 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector128) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->LISR >> 16) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 16;
- if (dma_isr_redir[10].dma_func)
- dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 3 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector12C) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->LISR >> 22) & STM32_DMA_ISR_MASK;
- DMA2->LIFCR = flags << 22;
- if (dma_isr_redir[11].dma_func)
- dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 4 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector130) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->HISR >> 0) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 0;
- if (dma_isr_redir[12].dma_func)
- dma_isr_redir[12].dma_func(dma_isr_redir[12].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 5 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector150) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->HISR >> 6) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 6;
- if (dma_isr_redir[13].dma_func)
- dma_isr_redir[13].dma_func(dma_isr_redir[13].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 6 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector154) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->HISR >> 16) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 16;
- if (dma_isr_redir[14].dma_func)
- dma_isr_redir[14].dma_func(dma_isr_redir[14].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief DMA2 stream 7 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector158) {
- uint32_t flags;
-
- OSAL_IRQ_PROLOGUE();
-
- flags = (DMA2->HISR >> 22) & STM32_DMA_ISR_MASK;
- DMA2->HIFCR = flags << 22;
- if (dma_isr_redir[15].dma_func)
- dma_isr_redir[15].dma_func(dma_isr_redir[15].dma_param, flags);
-
- OSAL_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions. */
-/*===========================================================================*/
-
-/**
- * @brief STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
- int i;
-
- dma_streams_mask = 0;
- for (i = 0; i < STM32_DMA_STREAMS; i++) {
- _stm32_dma_streams[i].stream->CR = 0;
- dma_isr_redir[i].dma_func = NULL;
- }
- DMA1->LIFCR = 0xFFFFFFFF;
- DMA1->HIFCR = 0xFFFFFFFF;
- DMA2->LIFCR = 0xFFFFFFFF;
- DMA2->HIFCR = 0xFFFFFFFF;
-}
-
-/**
- * @brief Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- * The function also enables the IRQ vector associated to the stream
- * and initializes its priority.
- * @pre The stream must not be already in use or an error is returned.
- * @post The stream is allocated and the default ISR handler redirected
- * to the specified function.
- * @post The stream ISR vector is enabled and its priority configured.
- * @post The stream must be freed using @p dmaStreamRelease() before it can
- * be reused with another peripheral.
- * @post The stream is in its post-reset state.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] priority IRQ priority mask for the DMA stream
- * @param[in] func handling function pointer, can be @p NULL
- * @param[in] param a parameter to be passed to the handling function
- * @return The operation status.
- * @retval FALSE no error, stream taken.
- * @retval TRUE error, stream already taken.
- *
- * @special
- */
-bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param) {
-
- osalDbgCheck(dmastp != NULL);
-
- /* Checks if the stream is already taken.*/
- if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
- return TRUE;
-
- /* Marks the stream as allocated.*/
- dma_isr_redir[dmastp->selfindex].dma_func = func;
- dma_isr_redir[dmastp->selfindex].dma_param = param;
- dma_streams_mask |= (1 << dmastp->selfindex);
-
- /* Enabling DMA clocks required by the current streams set.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
- rccEnableDMA1(FALSE);
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
- rccEnableDMA2(FALSE);
-
- /* Putting the stream in a safe state.*/
- dmaStreamDisable(dmastp);
- dmastp->stream->CR = STM32_DMA_CR_RESET_VALUE;
- dmastp->stream->FCR = STM32_DMA_FCR_RESET_VALUE;
-
- /* Enables the associated IRQ vector if a callback is defined.*/
- if (func != NULL)
- nvicEnableVector(dmastp->vector, priority);
-
- return FALSE;
-}
-
-/**
- * @brief Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- * Trying to release a unallocated stream is an illegal operation
- * and is trapped if assertions are enabled.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post The stream is again available.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
- osalDbgCheck(dmastp != NULL);
-
- /* Check if the streams is not taken.*/
- osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
- "not allocated");
-
- /* Disables the associated IRQ vector.*/
- nvicDisableVector(dmastp->vector);
-
- /* Marks the stream as not allocated.*/
- dma_streams_mask &= ~(1 << dmastp->selfindex);
-
- /* Shutting down clocks that are no more required, if any.*/
- if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
- rccDisableDMA1(FALSE);
- if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
- rccDisableDMA2(FALSE);
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_dma.h b/os/hal/ports/STM32/STM32F4xx/stm32_dma.h deleted file mode 100644 index ef71eb170..000000000 --- a/os/hal/ports/STM32/STM32F4xx/stm32_dma.h +++ /dev/null @@ -1,461 +0,0 @@ -/*
- ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-/**
- * @file STM32F4xx/stm32_dma.h
- * @brief Enhanced-DMA helper driver header.
- * @note This file requires definitions from the ST STM32F4xx header file
- * stm32f4xx.h.
- *
- * @addtogroup STM32F4xx_DMA
- * @{
- */
-
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants. */
-/*===========================================================================*/
-
-/**
- * @brief Total number of DMA streams.
- * @note This is the total number of streams among all the DMA units.
- */
-#define STM32_DMA_STREAMS 16
-
-/**
- * @brief Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK 0x3D
-
-/**
- * @brief Returns the channel associated to the specified stream.
- *
- * @param[in] id the unique numeric stream identifier
- * @param[in] c a stream/channel association word, one channel per
- * nibble
- * @return Returns the channel associated to the stream.
- */
-#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7) * 4)) & 7)
-
-/**
- * @brief Checks if a DMA priority is within the valid range.
- * @param[in] prio DMA priority
- *
- * @retval The check result.
- * @retval FALSE invalid DMA priority.
- * @retval TRUE correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
-
-/**
- * @brief Returns an unique numeric identifier for a DMA stream.
- *
- * @param[in] dma the DMA unit number
- * @param[in] stream the stream number
- * @return An unique numeric stream identifier.
- */
-#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream))
-
-/**
- * @brief Returns a DMA stream identifier mask.
- *
- *
- * @param[in] dma the DMA unit number
- * @param[in] stream the stream number
- * @return A DMA stream identifier mask.
- */
-#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
- (1 << STM32_DMA_STREAM_ID(dma, stream))
-
-/**
- * @brief Checks if a DMA stream unique identifier belongs to a mask.
- * @param[in] id the stream numeric identifier
- * @param[in] mask the stream numeric identifiers mask
- *
- * @retval The check result.
- * @retval FALSE id does not belong to the mask.
- * @retval TRUE id belongs to the mask.
- */
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
-
-/**
- * @name DMA streams identifiers
- * @{
- */
-/**
- * @brief Returns a pointer to a stm32_dma_stream_t structure.
- *
- * @param[in] id the stream numeric identifier
- * @return A pointer to the stm32_dma_stream_t constant structure
- * associated to the DMA stream.
- */
-#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id])
-
-#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0)
-#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1)
-#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2)
-#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3)
-#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4)
-#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5)
-#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6)
-#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7)
-#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8)
-#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9)
-#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10)
-#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11)
-#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12)
-#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13)
-#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14)
-#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15)
-/** @} */
-
-/**
- * @name CR register constants common to all DMA types
- * @{
- */
-#define STM32_DMA_CR_EN DMA_SxCR_EN
-#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE
-#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE
-#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE
-#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR
-#define STM32_DMA_CR_DIR_P2M 0
-#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0
-#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1
-#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC
-#define STM32_DMA_CR_PINC DMA_SxCR_PINC
-#define STM32_DMA_CR_MINC DMA_SxCR_MINC
-#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE 0
-#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE 0
-#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
- STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL
-#define STM32_DMA_CR_PL(n) ((n) << 16)
-/** @} */
-
-/**
- * @name CR register constants only found in STM32F2xx/STM32F4xx
- * @{
- */
-#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE
-#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL
-#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS
-#define STM32_DMA_CR_DBM DMA_SxCR_DBM
-#define STM32_DMA_CR_CT DMA_SxCR_CT
-#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST
-#define STM32_DMA_CR_PBURST_SINGLE 0
-#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0
-#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1
-#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)
-#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST
-#define STM32_DMA_CR_MBURST_SINGLE 0
-#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0
-#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1
-#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
-#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL
-#define STM32_DMA_CR_CHSEL(n) ((n) << 25)
-/** @} */
-
-/**
- * @name FCR register constants only found in STM32F2xx/STM32F4xx
- * @{
- */
-#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE
-#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS
-#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS
-#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH
-#define STM32_DMA_FCR_FTH_1Q 0
-#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0
-#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1
-#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1)
-/** @} */
-
-/**
- * @name Status flags passed to the ISR callbacks
- */
-#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0
-#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0
-#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0
-#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0
-#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks. */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types. */
-/*===========================================================================*/
-
-/**
- * @brief STM32 DMA stream descriptor structure.
- */
-typedef struct {
- DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */
- volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
- uint8_t ishift; /**< @brief Bits offset in xIFCR
- register. */
- uint8_t selfindex; /**< @brief Index to self in array. */
- uint8_t vector; /**< @brief Associated IRQ vector. */
-} stm32_dma_stream_t;
-
-/**
- * @brief STM32 DMA ISR function type.
- *
- * @param[in] p parameter for the registered function
- * @param[in] flags pre-shifted content of the xISR register, the bits
- * are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros. */
-/*===========================================================================*/
-
-/**
- * @name Macro Functions
- * @{
- */
-/**
- * @brief Associates a peripheral data register to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] addr value to be written in the PAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(dmastp, addr) { \
- (dmastp)->stream->PAR = (uint32_t)(addr); \
-}
-
-/**
- * @brief Associates a memory destination to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] addr value to be written in the M0AR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(dmastp, addr) { \
- (dmastp)->stream->M0AR = (uint32_t)(addr); \
-}
-
-/**
- * @brief Associates an alternate memory destination to a DMA stream.
- * @note This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] addr value to be written in the M1AR register
- *
- * @special
- */
-#define dmaStreamSetMemory1(dmastp, addr) { \
- (dmastp)->stream->M1AR = (uint32_t)(addr); \
-}
-
-/**
- * @brief Sets the number of transfers to be performed.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] size value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(dmastp, size) { \
- (dmastp)->stream->NDTR = (uint32_t)(size); \
-}
-
-/**
- * @brief Returns the number of transfers to be performed.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @return The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR))
-
-/**
- * @brief Programs the stream mode settings.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] mode value to be written in the CR register
- *
- * @special
- */
-#define dmaStreamSetMode(dmastp, mode) { \
- (dmastp)->stream->CR = (uint32_t)(mode); \
-}
-
-/**
- * @brief Programs the stream FIFO settings.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] mode value to be written in the FCR register
- *
- * @special
- */
-#define dmaStreamSetFIFO(dmastp, mode) { \
- (dmastp)->stream->FCR = (uint32_t)(mode); \
-}
-
-/**
- * @brief DMA stream enable.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(dmastp) { \
- (dmastp)->stream->CR |= STM32_DMA_CR_EN; \
-}
-
-/**
- * @brief DMA stream disable.
- * @details The function disables the specified stream, waits for the disable
- * operation to complete and then clears any pending interrupt.
- * @note This function can be invoked in both ISR or thread context.
- * @note Interrupts enabling flags are set to zero after this call, see
- * bug 3607518.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(dmastp) { \
- (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
- STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \
- STM32_DMA_CR_EN); \
- while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \
- ; \
- dmaStreamClearInterrupt(dmastp); \
-}
-
-/**
- * @brief DMA stream interrupt sources clear.
- * @note This function can be invoked in both ISR or thread context.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(dmastp) { \
- *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
-}
-
-/**
- * @brief Starts a memory to memory operation using the specified stream.
- * @note The default transfer data mode is "byte to byte" but it can be
- * changed by specifying extra options in the @p mode parameter.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- * @param[in] mode value to be written in the CCR register, this value
- * is implicitly ORed with:
- * - @p STM32_DMA_CR_MINC
- * - @p STM32_DMA_CR_PINC
- * - @p STM32_DMA_CR_DIR_M2M
- * - @p STM32_DMA_CR_EN
- * .
- * @param[in] src source address
- * @param[in] dst destination address
- * @param[in] n number of data units to copy
- */
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
- dmaStreamSetPeripheral(dmastp, src); \
- dmaStreamSetMemory0(dmastp, dst); \
- dmaStreamSetTransactionSize(dmastp, n); \
- dmaStreamSetMode(dmastp, (mode) | \
- STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
- STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
-}
-
-/**
- * @brief Polled wait for DMA transfer end.
- * @pre The stream must have been allocated using @p dmaStreamAllocate().
- * @post After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp pointer to a stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(dmastp) { \
- while ((dmastp)->stream->NDTR > 0) \
- ; \
- dmaStreamDisable(dmastp); \
-}
-/** @} */
-
-/*===========================================================================*/
-/* External declarations. */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
- void dmaInit(void);
- bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
- uint32_t priority,
- stm32_dmaisr_t func,
- void *param);
- void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STM32_DMA_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 54471483d..23ee93b21 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -68,6 +68,9 @@ /*===========================================================================*/
#if defined(STM32F429_439xx) || defined(STM32F427_437xx)
/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
#define STM32_HAS_ADC1 TRUE
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 4))
@@ -102,8 +105,42 @@ /* DMA attributes.*/
#define STM32_ADVANCED_DMA TRUE
+
#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
/* ETH attributes.*/
#define STM32_HAS_ETH TRUE
@@ -363,6 +400,9 @@ /*===========================================================================*/
#if defined(STM32F40_41xxx) || defined(STM32F2XX)
/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
#define STM32_HAS_ADC1 TRUE
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 4))
@@ -403,8 +443,42 @@ /* DMA attributes.*/
#define STM32_ADVANCED_DMA TRUE
+
#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
/* ETH attributes.*/
#if defined(STM32F405xx) || defined(STM32F415xx)
@@ -653,6 +727,9 @@ /*===========================================================================*/
#if defined(STM32F401xx)
/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
#define STM32_HAS_ADC1 TRUE
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 4))
@@ -687,8 +764,42 @@ /* DMA attributes.*/
#define STM32_ADVANCED_DMA TRUE
+
#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
@@ -890,6 +1001,9 @@ /*===========================================================================*/
#if defined(STM32F411xx)
/* ADC attributes.*/
+#define STM32_ADC_HANDLER Vector88
+#define STM32_ADC_NUMBER 18
+
#define STM32_HAS_ADC1 TRUE
#define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
STM32_DMA_STREAM_ID_MSK(2, 4))
@@ -915,8 +1029,42 @@ /* DMA attributes.*/
#define STM32_ADVANCED_DMA TRUE
+
#define STM32_HAS_DMA1 TRUE
+#define STM32_DMA1_CH0_HANDLER Vector6C
+#define STM32_DMA1_CH1_HANDLER Vector70
+#define STM32_DMA1_CH2_HANDLER Vector74
+#define STM32_DMA1_CH3_HANDLER Vector78
+#define STM32_DMA1_CH4_HANDLER Vector7C
+#define STM32_DMA1_CH5_HANDLER Vector80
+#define STM32_DMA1_CH6_HANDLER Vector84
+#define STM32_DMA1_CH7_HANDLER VectorFC
+#define STM32_DMA1_CH0_NUMBER 11
+#define STM32_DMA1_CH1_NUMBER 12
+#define STM32_DMA1_CH2_NUMBER 13
+#define STM32_DMA1_CH3_NUMBER 14
+#define STM32_DMA1_CH4_NUMBER 15
+#define STM32_DMA1_CH5_NUMBER 16
+#define STM32_DMA1_CH6_NUMBER 17
+#define STM32_DMA1_CH7_NUMBER 47
+
#define STM32_HAS_DMA2 TRUE
+#define STM32_DMA2_CH0_HANDLER Vector120
+#define STM32_DMA2_CH1_HANDLER Vector124
+#define STM32_DMA2_CH2_HANDLER Vector128
+#define STM32_DMA2_CH3_HANDLER Vector12C
+#define STM32_DMA2_CH4_HANDLER Vector130
+#define STM32_DMA2_CH5_HANDLER Vector150
+#define STM32_DMA2_CH6_HANDLER Vector154
+#define STM32_DMA2_CH7_HANDLER Vector158
+#define STM32_DMA2_CH0_NUMBER 56
+#define STM32_DMA2_CH1_NUMBER 57
+#define STM32_DMA2_CH2_NUMBER 58
+#define STM32_DMA2_CH3_NUMBER 59
+#define STM32_DMA2_CH4_NUMBER 60
+#define STM32_DMA2_CH5_NUMBER 68
+#define STM32_DMA2_CH6_NUMBER 69
+#define STM32_DMA2_CH7_NUMBER 70
/* ETH attributes.*/
#define STM32_HAS_ETH FALSE
|