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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2016-05-24 13:57:49 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2016-05-24 13:57:49 +0000 |
| commit | a3c37f98cce0829b9c1f6e00f01f6060b9494c26 (patch) | |
| tree | 08a4f4ca82e1959813d10fb85b0ed2ab565e07ce /os/hal/ports | |
| parent | b36f9f55856979ae773c8c676c0f6723440e52a1 (diff) | |
| download | ChibiOS-a3c37f98cce0829b9c1f6e00f01f6060b9494c26.tar.gz ChibiOS-a3c37f98cce0829b9c1f6e00f01f6060b9494c26.tar.bz2 ChibiOS-a3c37f98cce0829b9c1f6e00f01f6060b9494c26.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9508 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports')
| -rw-r--r-- | os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c | 16 | ||||
| -rw-r--r-- | os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h | 22 |
2 files changed, 38 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c index 40df845db..f914b6163 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c +++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c @@ -211,6 +211,22 @@ void qspi_lld_stop(QSPIDriver *qspip) { */
void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp) {
+#if STM32_USE_STM32_D1_WORKAROUND == TRUE
+ /* If it is a command without address and alternate phases then the command
+ is sent as an alternate byte, the command phase is suppressed.*/
+ if ((cmdp->cfg & (QSPI_CFG_ADDR_MODE_MASK | QSPI_CFG_ALT_MODE_MASK)) == 0U) {
+ uint32_t cfg;
+
+ /* The command mode field is copied in the alternate mode field. All
+ other fields are not used in this scenario.*/
+ cfg = (cmdp->cfg & QSPI_CFG_CMD_MODE_MASK) << 6U;
+
+ qspip->qspi->DLR = 0U;
+ qspip->qspi->ABR = cmdp->cfg & QSPI_CFG_CMD_MASK;
+ qspip->qspi->CCR = cfg;
+ return;
+ }
+#endif
qspip->qspi->DLR = 0U;
qspip->qspi->ABR = cmdp->alt;
qspip->qspi->CCR = cmdp->cfg;
diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h index c3a82d690..4465755bf 100644 --- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h +++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h @@ -31,6 +31,17 @@ /* Driver constants. */
/*===========================================================================*/
+/**
+ * @name DCR register options
+ * @{
+ */
+#define STM32_DCR_CK_MODE (1U << 0U)
+#define STM32_DCR_CSHT_MASK (7U << 8U)
+#define STM32_DCR_CSHT(n) ((n) << 8U)
+#define STM32_DCR_FSIZE_MASK (31U << 16U)
+#define STM32_DCR_FSIZE(n) ((n) << 16U)
+/** @} */
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -85,6 +96,17 @@ #if !defined(STM32_QSPI_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
#define STM32_QSPI_DMA_ERROR_HOOK(qspip) osalSysHalt("DMA failure")
#endif
+
+/**
+ * @brief Enables a workaround for a STM32L476 QUADSPI errata.
+ * @details The document DM00111498 states: "QUADSPI_BK1_IO1 is always an
+ * input when the command is sent in dual or quad SPI mode".
+ * This workaround makes commands without address or data phases
+ * to be sent as alternate bytes.
+ */
+#if !defined(STM32_USE_STM32_D1_WORKAROUND) || defined(__DOXYGEN__)
+#define STM32_USE_STM32_D1_WORKAROUND TRUE
+#endif
/** @} */
/*===========================================================================*/
|