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| author | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2016-05-13 12:46:36 +0000 |
|---|---|---|
| committer | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2016-05-13 12:46:36 +0000 |
| commit | 90a2b166cbcb5ca9a9110d579de30dac804e2f12 (patch) | |
| tree | c7e8ced6f593df2dd14092bc712c16bb344a1ec4 /os/hal/ports | |
| parent | 5ea09ccb8f302e4f5017edd1889521cd3c94be56 (diff) | |
| download | ChibiOS-90a2b166cbcb5ca9a9110d579de30dac804e2f12.tar.gz ChibiOS-90a2b166cbcb5ca9a9110d579de30dac804e2f12.tar.bz2 ChibiOS-90a2b166cbcb5ca9a9110d579de30dac804e2f12.zip | |
Added support for UART4 and UART5 in STM32L1xx Category 5 devices
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9476 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports')
| -rw-r--r-- | os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L1xx/stm32_isr.h | 5 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L1xx/stm32_rcc.h | 50 |
3 files changed, 58 insertions, 3 deletions
diff --git a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h index 14966216d..8f4c34efe 100644 --- a/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h +++ b/os/hal/ports/STM32/LLD/USARTv1/hal_uart_lld.h @@ -226,7 +226,8 @@ #error "UART4 not present in the selected device"
#endif
-#if !defined(STM32F2XX) && !defined(STM32F4XX)
+#if !defined(STM32F2XX) && !defined(STM32F4XX) && !defined(STM32L151xE) && \
+ !defined(STM32L152xE) && !defined(STM32L162xE)
#error "UART4 DMA access not supported in this platform"
#endif
#endif /* STM32_UART_USE_UART4 */
@@ -236,7 +237,8 @@ #error "UART5 not present in the selected device"
#endif
-#if !defined(STM32F2XX) && !defined(STM32F4XX)
+#if !defined(STM32F2XX) && !defined(STM32F4XX) && !defined(STM32L151xE) && \
+ !defined(STM32L152xE) && !defined(STM32L162xE)
#error "UART5 DMA access not supported in this platform"
#endif
#endif /* STM32_UART_USE_UART5 */
diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_isr.h b/os/hal/ports/STM32/STM32L1xx/stm32_isr.h index c36a430d2..7275c3a4f 100644 --- a/os/hal/ports/STM32/STM32L1xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32L1xx/stm32_isr.h @@ -75,11 +75,14 @@ #define STM32_USART1_HANDLER VectorD4
#define STM32_USART2_HANDLER VectorD8
#define STM32_USART3_HANDLER VectorDC
+#define STM32_UART4_HANDLER Vector100
+#define STM32_UART5_HANDLER Vector105
#define STM32_USART1_NUMBER 37
#define STM32_USART2_NUMBER 38
#define STM32_USART3_NUMBER 39
-
+#define STM32_UART4_NUMBER 48
+#define STM32_UART5_NUMBER 49
/*
* USB units.
*/
diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h index d13158c05..55ef32535 100644 --- a/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h @@ -744,6 +744,56 @@ * @api
*/
#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+
+/**
+ * @brief Enables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief Disables the UART4 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
+
+/**
+ * @brief Enables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief Disables the UART5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
/** @} */
/**
|