Flash infrastructure rework based on WSPI, not complete.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12320 110e8d01-0319-4d1e-a829-52ad28d1bb01

3 files changed, 93 insertions, 82 deletions

diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk b/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
index a4e4b610a..6d58d6bae 100644
--- a/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
+++ b/os/hal/ports/STM32/LLD/QUADSPIv1/driver.mk
@@ -2,8 +2,12 @@ ifeq ($(USE_SMART_BUILD),yes)
 ifneq ($(findstring HAL_USE_QSPI TRUE,$(HALCONF)),)

 PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c

 endif

+ifneq ($(findstring HAL_USE_WSPI TRUE,$(HALCONF)),)

+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c

+endif

 else

 PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c

+PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c

 endif

 

 PLATFORMINC += $(CHIBIOS)/os/hal/ports/STM32/LLD/QUADSPIv1

diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c
index f83a6acf6..3d6561ff6 100644
--- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c
+++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.c
@@ -129,7 +129,7 @@ void wspi_lld_init(void) {
 

 #if STM32_WSPI_USE_QUADSPI1

   wspiObjectInit(&WSPID1);

-  WSPID1.wspi       = QUADSPI;

+  WSPID1.qspi       = QUADSPI;

   WSPID1.dma        = STM32_DMA_STREAM(STM32_WSPI_QUADSPI1_DMA_STREAM);

   WSPID1.dmamode    = STM32_DMA_CR_CHSEL(QUADSPI1_DMA_CHANNEL) |

                       STM32_DMA_CR_PL(STM32_WSPI_QUADSPI1_DMA_PRIORITY) |

@@ -165,14 +165,14 @@ void wspi_lld_start(WSPIDriver *wspip) {
 #endif

 

     /* Common initializations.*/

-    dmaStreamSetPeripheral(wspip->dma, &wspip->wspi->DR);

+    dmaStreamSetPeripheral(wspip->dma, &wspip->qspi->DR);

   }

 

   /* WSPI setup and enable.*/

-  wspip->wspi->DCR = wspip->config->dcr;

-  wspip->wspi->CR  = ((STM32_WSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |

+  wspip->qspi->DCR = wspip->config->dcr;

+  wspip->qspi->CR  = ((STM32_WSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |

                       QUADSPI_CR_TCIE | QUADSPI_CR_DMAEN | QUADSPI_CR_EN;

-  wspip->wspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |

+  wspip->qspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |

                      QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;

 }

 

@@ -189,7 +189,7 @@ void wspi_lld_stop(WSPIDriver *wspip) {
   if (wspip->state == WSPI_READY) {

 

     /* WSPI disable.*/

-    wspip->wspi->CR = 0U;

+    wspip->qspi->CR = 0U;

 

     /* Releasing the DMA.*/

     dmaStreamRelease(wspip->dma);

@@ -218,23 +218,19 @@ void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) {
   /* If it is a command without address and alternate phases then the command

      is sent as an alternate byte, the command phase is suppressed.*/

   if ((cmdp->cfg & (WSPI_CFG_ADDR_MODE_MASK | WSPI_CFG_ALT_MODE_MASK)) == 0U) {

-    uint32_t cfg;

-

     /* The command mode field is copied in the alternate mode field. All

        other fields are not used in this scenario.*/

-    cfg = (cmdp->cfg  & WSPI_CFG_CMD_MODE_MASK) << 6U;

-

-    wspip->wspi->DLR = 0U;

-    wspip->wspi->ABR = cmdp->cfg & WSPI_CFG_CMD_MASK;

-    wspip->wspi->CCR = cfg;

+    wspip->qspi->DLR = 0U;

+    wspip->qspi->ABR = cmdp->cmd;

+    wspip->qspi->CCR = (cmdp->cfg  & WSPI_CFG_CMD_MODE_MASK) << 6U;

     return;

   }

 #endif

-  wspip->wspi->DLR = 0U;

-  wspip->wspi->ABR = cmdp->alt;

-  wspip->wspi->CCR = cmdp->cfg;

+  wspip->qspi->DLR = 0U;

+  wspip->qspi->ABR = cmdp->alt;

+  wspip->qspi->CCR = cmdp->cmd | cmdp->cfg;

   if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {

-    wspip->wspi->AR  = cmdp->addr;

+    wspip->qspi->AR  = cmdp->addr;

   }

 }

 

@@ -256,11 +252,11 @@ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp,
   dmaStreamSetTransactionSize(wspip->dma, n);

   dmaStreamSetMode(wspip->dma, wspip->dmamode | STM32_DMA_CR_DIR_M2P);

 

-  wspip->wspi->DLR = n - 1;

-  wspip->wspi->ABR = cmdp->alt;

-  wspip->wspi->CCR = cmdp->cfg;

+  wspip->qspi->DLR = n - 1;

+  wspip->qspi->ABR = cmdp->alt;

+  wspip->qspi->CCR = cmdp->cmd | cmdp->cfg;

   if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {

-    wspip->wspi->AR  = cmdp->addr;

+    wspip->qspi->AR  = cmdp->addr;

   }

 

   dmaStreamEnable(wspip->dma);

@@ -284,11 +280,13 @@ void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp,
   dmaStreamSetTransactionSize(wspip->dma, n);

   dmaStreamSetMode(wspip->dma, wspip->dmamode | STM32_DMA_CR_DIR_P2M);

 

-  wspip->wspi->DLR = n - 1;

-  wspip->wspi->ABR = cmdp->alt;

-  wspip->wspi->CCR = cmdp->cfg | QUADSPI_CCR_FMODE_0;

+  wspip->qspi->DLR = n - 1;

+  wspip->qspi->ABR = cmdp->alt;

+  wspip->qspi->CCR = cmdp->cmd | cmdp->cfg |

+                     QUADSPI_CCR_DUMMY_CYCLES(cmdp->dummy) |

+                     QUADSPI_CCR_FMODE_0;

   if ((cmdp->cfg & WSPI_CFG_ADDR_MODE_MASK) != WSPI_CFG_ADDR_MODE_NONE) {

-    wspip->wspi->AR  = cmdp->addr;

+    wspip->qspi->AR  = cmdp->addr;

   }

 

   dmaStreamEnable(wspip->dma);

@@ -312,13 +310,14 @@ void wspi_lld_map_flash(WSPIDriver *wspip,
                         uint8_t **addrp) {

 

   /* Disabling the DMA request while in memory mapped mode.*/

-  wspip->wspi->CR &= ~QUADSPI_CR_DMAEN;

+  wspip->qspi->CR &= ~QUADSPI_CR_DMAEN;

 

   /* Starting memory mapped mode using the passed parameters.*/

-  wspip->wspi->DLR = 0;

-  wspip->wspi->ABR = 0;

-  wspip->wspi->AR  = 0;

-  wspip->wspi->CCR = cmdp->cfg | QUADSPI_CCR_FMODE_1 | QUADSPI_CCR_FMODE_0;

+  wspip->qspi->DLR = 0;

+  wspip->qspi->ABR = 0;

+  wspip->qspi->AR  = 0;

+  wspip->qspi->CCR = cmdp->cmd | cmdp->cfg |

+                     QUADSPI_CCR_FMODE_1 | QUADSPI_CCR_FMODE_0;

 

   /* Mapped flash absolute base address.*/

   if (addrp != NULL) {

@@ -338,12 +337,12 @@ void wspi_lld_map_flash(WSPIDriver *wspip,
 void wspi_lld_unmap_flash(WSPIDriver *wspip) {

 

   /* Aborting memory mapped mode.*/

-  wspip->wspi->CR |= QUADSPI_CR_ABORT;

-  while ((wspip->wspi->CR & QUADSPI_CR_ABORT) != 0U) {

+  wspip->qspi->CR |= QUADSPI_CR_ABORT;

+  while ((wspip->qspi->CR & QUADSPI_CR_ABORT) != 0U) {

   }

 

   /* Re-enabling DMA request, we are going back to indirect mode.*/

-  wspip->wspi->CR |= QUADSPI_CR_DMAEN;

+  wspip->qspi->CR |= QUADSPI_CR_DMAEN;

 }

 #endif /* WSPI_SUPPORTS_MEMMAP == TRUE */

 

diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.h b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.h
index 456b0308d..ce58a6945 100644
--- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.h
+++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_wspi_lld.h
@@ -53,54 +53,62 @@
  *          .

  * @{

  */

-#define WSPI_CFG_INSTRUCTION_MODE_MASK          (3LU << 8LU)

-#define WSPI_CFG_INSTRUCTION_MODE_NONE          (0LU << 8LU)

-#define WSPI_CFG_INSTRUCTION_MODE_ONE_LINES     (1LU << 8LU)

-#define WSPI_CFG_INSTRUCTION_MODE_TWO_LINES     (2LU << 8LU)

-#define WSPI_CFG_INSTRUCTION_MODE_FOUR_LINES    (3LU << 8LU)

-

-#define WSPI_CFG_INSTRUCTION_DDR                (1LU << 31LU)

-

-#define WSPI_CFG_INSTRUCTION_SIZE_MASK          0LU

-#define WSPI_CFG_INSTRUCTION_SIZE_8             0LU

-

-#define WSPI_CFG_ADDR_MODE_MASK                 (3LU << 10LU)

-#define WSPI_CFG_ADDR_MODE_NONE                 (0LU << 10LU)

-#define WSPI_CFG_ADDR_MODE_ONE_LINE             (1LU << 10LU)

-#define WSPI_CFG_ADDR_MODE_TWO_LINES            (2LU << 10LU)

-#define WSPI_CFG_ADDR_MODE_FOUR_LINES           (3LU << 10LU)

-

-#define WSPI_CFG_ADDR_DDR                       (1LU << 31LU)

-

-#define WSPI_CFG_ADDR_SIZE_MASK                 (3LU << 12LU)

-#define WSPI_CFG_ADDR_SIZE_8                    (0LU << 12LU)

-#define WSPI_CFG_ADDR_SIZE_16                   (1LU << 12LU)

-#define WSPI_CFG_ADDR_SIZE_24                   (2LU << 12LU)

-#define WSPI_CFG_ADDR_SIZE_32                   (3LU << 12LU)

-

-#define WSPI_CFG_ALT_MODE_MASK                  (3LU << 14LU)

-#define WSPI_CFG_ALT_MODE_NONE                  (0LU << 14LU)

-#define WSPI_CFG_ALT_MODE_ONE_LINE              (1LU << 14LU)

-#define WSPI_CFG_ALT_MODE_TWO_LINES             (2LU << 14LU)

-#define WSPI_CFG_ALT_MODE_FOUR_LINES            (3LU << 14LU)

-

-#define WSPI_CFG_ALT_DDR                        (1LU << 31LU)

-

-#define WSPI_CFG_ALT_SIZE_MASK                  (3LU << 16LU)

-#define WSPI_CFG_ALT_SIZE_8                     (0LU << 16LU)

-#define WSPI_CFG_ALT_SIZE_16                    (1LU << 16LU)

-#define WSPI_CFG_ALT_SIZE_24                    (2LU << 16LU)

-#define WSPI_CFG_ALT_SIZE_32                    (3LU << 16LU)

-

-#define WSPI_CFG_DATA_MODE_MASK                 (3LU << 24LU)

-#define WSPI_CFG_DATA_MODE_NONE                 (0LU << 24LU)

-#define WSPI_CFG_DATA_MODE_ONE_LINE             (1LU << 24LU)

-#define WSPI_CFG_DATA_MODE_TWO_LINES            (2LU << 24LU)

-#define WSPI_CFG_DATA_MODE_FOUR_LINES           (3LU << 24LU)

-

-#define WSPI_CFG_DATA_DDR                       (1LU << 31LU)

-

-#define WSPI_CFG_SIOO                           (1LU << 28LU)

+#define WSPI_CFG_CMD_MODE_MASK              (3LU << 8LU)

+#define WSPI_CFG_CMD_MODE_NONE              (0LU << 8LU)

+#define WSPI_CFG_CMD_MODE_ONE_LINE          (1LU << 8LU)

+#define WSPI_CFG_CMD_MODE_TWO_LINES         (2LU << 8LU)

+#define WSPI_CFG_CMD_MODE_FOUR_LINES        (3LU << 8LU)

+

+#define WSPI_CFG_CMD_DDR                    (1LU << 31LU)

+

+#define WSPI_CFG_CMD_SIZE_MASK              0LU

+#define WSPI_CFG_CMD_SIZE_8                 0LU

+

+#define WSPI_CFG_ADDR_MODE_MASK             (3LU << 10LU)

+#define WSPI_CFG_ADDR_MODE_NONE             (0LU << 10LU)

+#define WSPI_CFG_ADDR_MODE_ONE_LINE         (1LU << 10LU)

+#define WSPI_CFG_ADDR_MODE_TWO_LINES        (2LU << 10LU)

+#define WSPI_CFG_ADDR_MODE_FOUR_LINES       (3LU << 10LU)

+

+#define WSPI_CFG_ADDR_DDR                   (1LU << 31LU)

+

+#define WSPI_CFG_ADDR_SIZE_MASK             (3LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_8                (0LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_16               (1LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_24               (2LU << 12LU)

+#define WSPI_CFG_ADDR_SIZE_32               (3LU << 12LU)

+

+#define WSPI_CFG_ALT_MODE_MASK              (3LU << 14LU)

+#define WSPI_CFG_ALT_MODE_NONE              (0LU << 14LU)

+#define WSPI_CFG_ALT_MODE_ONE_LINE          (1LU << 14LU)

+#define WSPI_CFG_ALT_MODE_TWO_LINES         (2LU << 14LU)

+#define WSPI_CFG_ALT_MODE_FOUR_LINES        (3LU << 14LU)

+

+#define WSPI_CFG_ALT_DDR                    (1LU << 31LU)

+

+#define WSPI_CFG_ALT_SIZE_MASK              (3LU << 16LU)

+#define WSPI_CFG_ALT_SIZE_8                 (0LU << 16LU)

+#define WSPI_CFG_ALT_SIZE_16                (1LU << 16LU)

+#define WSPI_CFG_ALT_SIZE_24                (2LU << 16LU)

+#define WSPI_CFG_ALT_SIZE_32                (3LU << 16LU)

+

+#define WSPI_CFG_DATA_MODE_MASK             (3LU << 24LU)

+#define WSPI_CFG_DATA_MODE_NONE             (0LU << 24LU)

+#define WSPI_CFG_DATA_MODE_ONE_LINE         (1LU << 24LU)

+#define WSPI_CFG_DATA_MODE_TWO_LINES        (2LU << 24LU)

+#define WSPI_CFG_DATA_MODE_FOUR_LINES       (3LU << 24LU)

+

+#define WSPI_CFG_DATA_DDR                   (1LU << 31LU)

+

+#define WSPI_CFG_SIOO                       (1LU << 28LU)

+/** @} */

+

+/**

+ * @name    Helpers for CCR register.

+ * @{

+ */

+#define QUADSPI_CCR_DUMMY_CYCLES_MASK       (0x1FLU << 18LU)

+#define QUADSPI_CCR_DUMMY_CYCLES(n)         ((n) << 18LU)

 /** @} */

 

 /**

@@ -239,7 +247,7 @@ struct hal_wspi_config {
   /**

    * @brief   Operation complete callback or @p NULL.

    */

-  wspicallback_t             end_cb;

+  wspicallback_t            end_cb;

   /* End of the mandatory fields.*/

   /**

    * @brief   DCR register initialization data.