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| author | Uladzimir Pylinski <barthess@yandex.ru> | 2015-03-13 20:16:14 +0000 |
|---|---|---|
| committer | Uladzimir Pylinski <barthess@yandex.ru> | 2015-03-13 20:16:14 +0000 |
| commit | 383df301227d6de830597905b5f20ccb3664dca0 (patch) | |
| tree | e030c7e0a3b732831e50735956246e7fcb887c9c /os/hal/ports | |
| parent | 28b2143a444a29f9739d0016633c01b9273cf88f (diff) | |
| download | ChibiOS-383df301227d6de830597905b5f20ccb3664dca0.tar.gz ChibiOS-383df301227d6de830597905b5f20ccb3664dca0.tar.bz2 ChibiOS-383df301227d6de830597905b5f20ccb3664dca0.zip | |
STM32F4xx. Added interrupt handler definitions and RCC switch macros for TIM10, TIM11.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7769 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_isr.h | 4 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_rcc.h | 54 |
2 files changed, 58 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h index 355652413..1c9a90a0a 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_isr.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_isr.h @@ -106,8 +106,10 @@ #define STM32_TIM8_UP_HANDLER VectorF0
#define STM32_TIM8_CC_HANDLER VectorF8
#define STM32_TIM9_HANDLER VectorA0
+#define STM32_TIM10_HANDLER VectorA4 /* Note: same as STM32_TIM1_UP */
#define STM32_TIM11_HANDLER VectorA8
#define STM32_TIM12_HANDLER VectorEC
+#define STM32_TIM13_HANDLER VectorF0 /* Note: same as STM32_TIM8_UP */
#define STM32_TIM14_HANDLER VectorF4
#define STM32_TIM1_UP_NUMBER 25
@@ -121,8 +123,10 @@ #define STM32_TIM8_UP_NUMBER 44
#define STM32_TIM8_CC_NUMBER 46
#define STM32_TIM9_NUMBER 24
+#define STM32_TIM10_NUMBER 25 /* Note: same as STM32_TIM1_UP */
#define STM32_TIM11_NUMBER 26
#define STM32_TIM12_NUMBER 43
+#define STM32_TIM13_NUMBER 44 /* Note: same as STM32_TIM8_UP */
#define STM32_TIM14_NUMBER 45
/*
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h index cb0762c6d..8e1dc25a9 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_rcc.h @@ -1114,6 +1114,33 @@ #define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST)
/**
+ * @brief Enables the TIM10 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp)
+
+/**
+ * @brief Disables the TIM10 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp)
+
+/**
+ * @brief Resets the TIM10 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST)
+
+/**
* @brief Enables the TIM11 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
@@ -1168,6 +1195,33 @@ #define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)
/**
+ * @brief Enables the TIM13 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Disables the TIM13 peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Resets the TIM13 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
+
+/**
* @brief Enables the TIM14 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
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