Added support for STM32F410Rx,

Added board files for ST_NUCLEO64_F410RB
Added demo for STM32/RT-STM32F410RB-NUCLEO64

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9392 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 298 insertions, 3 deletions

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 7f02aaa30..bbfbad2b4 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -114,9 +114,12 @@ static void hal_lld_backup_domain_init(void) {
 void hal_lld_init(void) {

 

   /* Reset of all peripherals. AHB3 is not reseted because it could have

-     been initialized in the board initialization file (board.c).*/

+     been initialized in the board initialization file (board.c) and AHB2 is not

+     present in STM32F410. */

   rccResetAHB1(~0);

+#if !defined(STM32F410xx)

   rccResetAHB2(~0);

+#endif

   rccResetAPB1(~RCC_APB1RSTR_PWRRST);

   rccResetAPB2(~0);

 

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
index 1fa6159b9..90e00c520 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -98,6 +98,12 @@
 #elif defined(STM32F401xE)

 #define PLATFORM_NAME           "STM32F401xE High Performance with DSP and FPU"

 

+#elif defined(STM32F410Cx)

+#define PLATFORM_NAME           "STM32F410Cx High Performance with DSP and FPU"

+

+#elif defined(STM32F410Rx)

+#define PLATFORM_NAME           "STM32F410Rx High Performance with DSP and FPU"

+

 #elif defined(STM32F411xE)

 #define PLATFORM_NAME           "STM32F411xE High Performance with DSP and FPU"

 

@@ -252,6 +258,26 @@
 #define STM32_SPII2S_MAX        42000000

 #endif

 

+#if defined(STM32F410xx)

+#define STM32_SYSCLK_MAX        100000000

+#define STM32_HSECLK_MAX        26000000

+#define STM32_HSECLK_BYP_MAX    50000000

+#define STM32_HSECLK_MIN        4000000

+#define STM32_HSECLK_BYP_MIN    1000000

+#define STM32_LSECLK_MAX        32768

+#define STM32_LSECLK_BYP_MAX    1000000

+#define STM32_LSECLK_MIN        32768

+#define STM32_PLLIN_MAX         2100000

+#define STM32_PLLIN_MIN         950000

+#define STM32_PLLVCO_MAX        432000000

+#define STM32_PLLVCO_MIN        100000000

+#define STM32_PLLOUT_MAX        100000000

+#define STM32_PLLOUT_MIN        24000000

+#define STM32_PCLK1_MAX         50000000

+#define STM32_PCLK2_MAX         100000000

+#define STM32_SPII2S_MAX        50000000

+#endif

+

 #if defined(STM32F411xx)

 #define STM32_SYSCLK_MAX        100000000

 #define STM32_HSECLK_MAX        26000000

@@ -850,7 +876,7 @@
 #error "invalid VDD voltage specified"

 #endif

 

-#elif defined(STM32F411xx)

+#elif defined(STM32F410xx) || defined(STM32F411xx)

 #if (STM32_VDD >= 270) && (STM32_VDD <= 360)

 #define STM32_0WS_THRESHOLD         30000000

 #define STM32_1WS_THRESHOLD         64000000

@@ -1202,7 +1228,7 @@
 #endif

 #define STM32_OVERDRIVE_REQUIRED    FALSE

 

-#elif defined(STM32F411xx)

+#elif defined(STM32F410xx) || defined(STM32F411xx)

 #if STM32_SYSCLK <= 64000000

 #define STM32_VOS                   STM32_VOS_SCALE3

 #elif STM32_SYSCLK <= 84000000

diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
index 78f389b38..ecff41099 100644
--- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h
@@ -49,6 +49,11 @@
 #define STM32F401xx

 #define STM32F4XX

 

+#elif defined(STM32F410Cx) || defined(STM32F410Rx)

+#define STM32F410C_410Rx

+#define STM32F410xx

+#define STM32F4XX

+

 #elif defined(STM32F411xE)

 #define STM32F411xx

 #define STM32F4XX

@@ -1731,6 +1736,267 @@
 #endif /* defined(STM32F401xx) */

 

 /*===========================================================================*/

+/* STM32F410Cx, STM32F410Rx.                                                 */

+/*===========================================================================*/

+#if defined(STM32F410C_410Rx)

+/* ADC attributes.*/

+#define STM32_ADC_HANDLER                   Vector88

+#define STM32_ADC_NUMBER                    18

+

+#define STM32_HAS_ADC1                      TRUE

+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(2, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 4))

+#define STM32_ADC1_DMA_CHN                  0x00000000

+

+#define STM32_HAS_ADC2                      FALSE

+#define STM32_HAS_ADC3                      FALSE

+#define STM32_HAS_ADC4                      FALSE

+

+#define STM32_HAS_SDADC1                    FALSE

+#define STM32_HAS_SDADC2                    FALSE

+#define STM32_HAS_SDADC3                    FALSE

+

+/* CAN attributes.*/

+#define STM32_HAS_CAN1                      FALSE

+#define STM32_HAS_CAN2                      FALSE

+

+/* DAC attributes.*/

+#define STM32_HAS_DAC1_CH1                  TRUE

+#define STM32_DAC1_CH1_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_DAC1_CH1_DMA_CHN              0x00700000

+

+#define STM32_HAS_DAC1_CH2                  FALSE

+#define STM32_HAS_DAC2_CH1                  FALSE

+#define STM32_HAS_DAC2_CH2                  FALSE

+

+/* DMA attributes.*/

+#define STM32_ADVANCED_DMA                  TRUE

+#define STM32_DMA_CACHE_HANDLING            FALSE

+

+#define STM32_HAS_DMA1                      TRUE

+#define STM32_DMA1_CH0_HANDLER              Vector6C

+#define STM32_DMA1_CH1_HANDLER              Vector70

+#define STM32_DMA1_CH2_HANDLER              Vector74

+#define STM32_DMA1_CH3_HANDLER              Vector78

+#define STM32_DMA1_CH4_HANDLER              Vector7C

+#define STM32_DMA1_CH5_HANDLER              Vector80

+#define STM32_DMA1_CH6_HANDLER              Vector84

+#define STM32_DMA1_CH7_HANDLER              VectorFC

+#define STM32_DMA1_CH0_NUMBER               11

+#define STM32_DMA1_CH1_NUMBER               12

+#define STM32_DMA1_CH2_NUMBER               13

+#define STM32_DMA1_CH3_NUMBER               14

+#define STM32_DMA1_CH4_NUMBER               15

+#define STM32_DMA1_CH5_NUMBER               16

+#define STM32_DMA1_CH6_NUMBER               17

+#define STM32_DMA1_CH7_NUMBER               47

+

+#define STM32_HAS_DMA2                      TRUE

+#define STM32_DMA2_CH0_HANDLER              Vector120

+#define STM32_DMA2_CH1_HANDLER              Vector124

+#define STM32_DMA2_CH2_HANDLER              Vector128

+#define STM32_DMA2_CH3_HANDLER              Vector12C

+#define STM32_DMA2_CH4_HANDLER              Vector130

+#define STM32_DMA2_CH5_HANDLER              Vector150

+#define STM32_DMA2_CH6_HANDLER              Vector154

+#define STM32_DMA2_CH7_HANDLER              Vector158

+#define STM32_DMA2_CH0_NUMBER               56

+#define STM32_DMA2_CH1_NUMBER               57

+#define STM32_DMA2_CH2_NUMBER               58

+#define STM32_DMA2_CH3_NUMBER               59

+#define STM32_DMA2_CH4_NUMBER               60

+#define STM32_DMA2_CH5_NUMBER               68

+#define STM32_DMA2_CH6_NUMBER               69

+#define STM32_DMA2_CH7_NUMBER               70

+

+/* ETH attributes.*/

+#define STM32_HAS_ETH                       FALSE

+

+/* EXTI attributes.*/

+#define STM32_EXTI_NUM_LINES                23

+#define STM32_EXTI_IMR_MASK                 0x00000000U

+

+/* GPIO attributes.*/

+#define STM32_HAS_GPIOA                     TRUE

+#define STM32_HAS_GPIOB                     TRUE

+#define STM32_HAS_GPIOC                     TRUE

+#define STM32_HAS_GPIOD                     FALSE

+#define STM32_HAS_GPIOE                     FALSE

+#define STM32_HAS_GPIOH                     TRUE

+#define STM32_HAS_GPIOF                     FALSE

+#define STM32_HAS_GPIOG                     FALSE

+#define STM32_HAS_GPIOI                     FALSE

+#define STM32_HAS_GPIOJ                     FALSE

+#define STM32_HAS_GPIOK                     FALSE

+#define STM32_GPIO_EN_MASK                  (RCC_AHB1ENR_GPIOAEN |          \

+                                             RCC_AHB1ENR_GPIOBEN |          \

+                                             RCC_AHB1ENR_GPIOCEN |          \

+                                             RCC_AHB1ENR_GPIOHEN)

+

+/* I2C attributes.*/

+#define STM32_HAS_I2C1                      TRUE

+#define STM32_I2C1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 5))

+#define STM32_I2C1_RX_DMA_CHN               0x00100001

+#define STM32_I2C1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 6))

+#define STM32_I2C1_TX_DMA_CHN               0x11000000

+

+#define STM32_HAS_I2C2                      TRUE

+#define STM32_I2C2_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 2) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_I2C2_RX_DMA_CHN               0x00007700

+#define STM32_I2C2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 7)

+#define STM32_I2C2_TX_DMA_CHN               0x70000000

+

+#define STM32_HAS_I2C3                      FALSE

+

+#define STM32_HAS_I2C4                      FALSE

+#define STM32_I2C4_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 0)) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 3))

+#define STM32_I2C4_RX_DMA_CHN               0x00002007

+#define STM32_I2C4_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(1, 7)) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 1))

+#define STM32_I2C4_TX_DMA_CHN               0x00040020

+

+/* RTC attributes.*/

+#define STM32_HAS_RTC                       TRUE

+#define STM32_RTC_HAS_SUBSECONDS            TRUE

+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE

+#define STM32_RTC_NUM_ALARMS                2

+#define STM32_RTC_HAS_INTERRUPTS            FALSE

+

+/* SDIO attributes.*/

+#define STM32_HAS_SDIO                      FALSE

+

+/* SPI attributes.*/

+#define STM32_HAS_SPI1                      TRUE

+#define STM32_SPI1_SUPPORTS_I2S             FALSE

+#define STM32_SPI1_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 0) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 2))

+#define STM32_SPI1_RX_DMA_CHN               0x00000303

+#define STM32_SPI1_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 2) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 3))

+#define STM32_SPI1_TX_DMA_CHN               0x00003200

+

+#define STM32_HAS_SPI2                      TRUE

+#define STM32_SPI2_SUPPORTS_I2S             TRUE

+#define STM32_SPI2_I2S_FULLDUPLEX           TRUE

+#define STM32_SPI2_RX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 3)

+#define STM32_SPI2_RX_DMA_CHN               0x00000000

+#define STM32_SPI2_TX_DMA_MSK               STM32_DMA_STREAM_ID_MSK(1, 4)

+#define STM32_SPI2_TX_DMA_CHN               0x00000000

+

+#define STM32_HAS_SPI5                      TRUE

+#define STM32_SPI5_SUPPORTS_I2S             TRUE

+#define STM32_SPI5_RX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 3) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_SPI5_RX_DMA_CHN               0x00702000

+#define STM32_SPI5_TX_DMA_MSK               (STM32_DMA_STREAM_ID_MSK(2, 4) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 6))

+#define STM32_SPI5_TX_DMA_CHN               0x07020000

+

+#define STM32_HAS_SPI3                      FALSE

+#define STM32_HAS_SPI4                      FALSE

+#define STM32_HAS_SPI6                      FALSE

+

+/* TIM attributes.*/

+#define STM32_TIM_MAX_CHANNELS              4

+

+#define STM32_HAS_TIM1                      TRUE

+#define STM32_TIM1_IS_32BITS                FALSE

+#define STM32_TIM1_CHANNELS                 4

+

+#define STM32_HAS_TIM5                      TRUE

+#define STM32_TIM5_IS_32BITS                TRUE

+#define STM32_TIM5_CHANNELS                 4

+

+#define STM32_HAS_TIM6                      TRUE

+#define STM32_TIM6_IS_32BITS                FALSE

+#define STM32_TIM6_CHANNELS                 0

+

+#define STM32_HAS_TIM9                      TRUE

+#define STM32_TIM9_IS_32BITS                FALSE

+#define STM32_TIM9_CHANNELS                 2

+

+#define STM32_HAS_TIM11                     TRUE

+#define STM32_TIM11_IS_32BITS               FALSE

+#define STM32_TIM11_CHANNELS                1

+

+#define STM32_HAS_TIM2                      FALSE

+#define STM32_HAS_TIM3                      FALSE

+#define STM32_HAS_TIM4                      FALSE

+#define STM32_HAS_TIM7                      FALSE

+#define STM32_HAS_TIM8                      FALSE

+#define STM32_HAS_TIM10                     FALSE

+#define STM32_HAS_TIM12                     FALSE

+#define STM32_HAS_TIM13                     FALSE

+#define STM32_HAS_TIM14                     FALSE

+#define STM32_HAS_TIM15                     FALSE

+#define STM32_HAS_TIM16                     FALSE

+#define STM32_HAS_TIM17                     FALSE

+#define STM32_HAS_TIM18                     FALSE

+#define STM32_HAS_TIM19                     FALSE

+#define STM32_HAS_TIM20                     FALSE

+#define STM32_HAS_TIM21                     FALSE

+#define STM32_HAS_TIM22                     FALSE

+

+/* USART attributes.*/

+#define STM32_HAS_USART1                    TRUE

+#define STM32_USART1_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 2) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 5))

+#define STM32_USART1_RX_DMA_CHN             0x00400400

+#define STM32_USART1_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(2, 7)

+#define STM32_USART1_TX_DMA_CHN             0x40000000

+

+#define STM32_HAS_USART2                    TRUE

+#define STM32_USART2_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(1, 5) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 7))

+#define STM32_USART2_RX_DMA_CHN             0x60400000

+#define STM32_USART2_TX_DMA_MSK             STM32_DMA_STREAM_ID_MSK(1, 6)

+#define STM32_USART2_TX_DMA_CHN             0x04000000

+

+#define STM32_HAS_USART3                    FALSE

+#define STM32_HAS_UART4                     FALSE

+#define STM32_HAS_UART5                     FALSE

+

+#define STM32_HAS_USART6                    TRUE

+#define STM32_USART6_RX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 2))

+#define STM32_USART6_RX_DMA_CHN             0x00000550

+#define STM32_USART6_TX_DMA_MSK             (STM32_DMA_STREAM_ID_MSK(2, 6) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 7))

+#define STM32_USART6_TX_DMA_CHN             0x55000000

+

+#define STM32_HAS_UART7                     FALSE

+#define STM32_HAS_UART8                     FALSE

+#define STM32_HAS_LPUART1                   FALSE

+

+/* USB attributes.*/

+#define STM32_HAS_USB                       FALSE

+#define STM32_HAS_OTG1                      FALSE

+#define STM32_HAS_OTG2                      FALSE

+

+/* IWDG attributes.*/

+#define STM32_HAS_IWDG                      TRUE

+#define STM32_IWDG_IS_WINDOWED              FALSE

+

+/* LTDC attributes.*/

+#define STM32_HAS_LTDC                      FALSE

+

+/* DMA2D attributes.*/

+#define STM32_HAS_DMA2D                     FALSE

+

+/* FSMC attributes.*/

+#define STM32_HAS_FSMC                      FALSE

+

+/* CRC attributes.*/

+#define STM32_HAS_CRC                       TRUE

+#define STM32_CRC_PROGRAMMABLE              FALSE

+

+#endif /* defined(STM32F410C_410Rx) */

+

+/*===========================================================================*/

 /* STM32F411xE.                                                              */

 /*===========================================================================*/

 #if defined(STM32F411xx)