git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6276 35acf78f-673a-0410-8e92-d51de3d6d3f4

8 files changed, 280 insertions, 316 deletions

diff --git a/os/hal/ports/STM32F37x/adc_lld.c b/os/hal/ports/STM32F37x/adc_lld.c
index ebb6da7ec..72514ded6 100644
--- a/os/hal/ports/STM32F37x/adc_lld.c
+++ b/os/hal/ports/STM32F37x/adc_lld.c
@@ -15,14 +15,13 @@
 */

 

 /**

- * @file    STM32F4xx/adc_lld.c

- * @brief   STM32F4xx/STM32F2xx ADC subsystem low level driver source.

+ * @file    STM32F37x/adc_lld.c

+ * @brief   STM32F37x ADC subsystem low level driver source.

  *

  * @addtogroup ADC

  * @{

  */

 

-#include "ch.h"

 #include "hal.h"

 

 #if HAL_USE_ADC || defined(__DOXYGEN__)

@@ -132,7 +131,7 @@ static void adc_lld_reconfig(ADCDriver *adcp) {
 #endif /* STM32_ADC_USE_SDADC */

 #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC

 else {

-    chDbgAssert(FALSE, "adc_lld_start(), #5", "invalid state");

+    osalDbgAssert(FALSE, "invalid state");

   }

 #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */

 }

@@ -227,16 +226,16 @@ static void sdadc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector88) {

+OSAL_IRQ_HANDLER(Vector88) {

   uint32_t sr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   sr  = ADC1->SR;

   ADC1->SR = 0;

   adc_lld_serve_interrupt(&ADCD1, sr);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif /* STM32_ADC_USE_ADC1 */

 

@@ -246,16 +245,16 @@ CH_IRQ_HANDLER(Vector88) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector134) {

+OSAL_IRQ_HANDLER(Vector134) {

   uint32_t isr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   isr  = SDADC1->ISR;

   SDADC1->CLRISR = isr;

   sdadc_lld_serve_interrupt(&SDADCD1, isr);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif /* STM32_ADC_USE_SDADC1 */

 

@@ -265,16 +264,16 @@ CH_IRQ_HANDLER(Vector134) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector138) {

+OSAL_IRQ_HANDLER(Vector138) {

   uint32_t isr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   isr  = SDADC2->ISR;

   SDADC2->CLRISR = isr;

   sdadc_lld_serve_interrupt(&SDADCD2, isr);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif /* STM32_ADC_USE_SDADC2 */

 

@@ -284,16 +283,16 @@ CH_IRQ_HANDLER(Vector138) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector13C) {

+OSAL_IRQ_HANDLER(Vector13C) {

   uint32_t isr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   isr  = SDADC3->ISR;

   SDADC3->CLRISR = isr;

   sdadc_lld_serve_interrupt(&SDADCD3, isr);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif /* STM32_ADC_USE_SDADC3 */

 

@@ -322,7 +321,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

                   STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

-  nvicEnableVector(ADC1_IRQn, CORTEX_PRIORITY_MASK(STM32_ADC_IRQ_PRIORITY));

+  nvicEnableVector(ADC1_IRQn, STM32_ADC_IRQ_PRIORITY);

 #endif

 

 #if STM32_ADC_USE_SDADC1

@@ -339,8 +338,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

                   STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

-  nvicEnableVector(SDADC1_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_ADC_SDADC1_IRQ_PRIORITY));

+  nvicEnableVector(SDADC1_IRQn, STM32_ADC_SDADC1_IRQ_PRIORITY);

 #endif

 

 #if STM32_ADC_USE_SDADC2

@@ -357,8 +355,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

                   STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

-  nvicEnableVector(SDADC2_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_ADC_SDADC2_IRQ_PRIORITY));

+  nvicEnableVector(SDADC2_IRQn, STM32_ADC_SDADC2_IRQ_PRIORITY);

 #endif

 

 #if STM32_ADC_USE_SDADC3

@@ -375,8 +372,7 @@ void adc_lld_init(void) {
                   STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

                   STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

                   STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

-  nvicEnableVector(SDADC3_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_ADC_SDADC3_IRQ_PRIORITY));

+  nvicEnableVector(SDADC3_IRQn, STM32_ADC_SDADC3_IRQ_PRIORITY);

 #endif

 }

 

@@ -396,12 +392,11 @@ void adc_lld_start(ADCDriver *adcp) {
   if (adcp->state == ADC_STOP) {

 #if STM32_ADC_USE_ADC1

     if (&ADCD1 == adcp) {

-      bool_t b;

-      b = dmaStreamAllocate(adcp->dmastp,

-                            STM32_ADC_ADC1_DMA_IRQ_PRIORITY,

-                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

-                            (void *)adcp);

-      chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");

+      bool b = dmaStreamAllocate(adcp->dmastp,

+                                 STM32_ADC_ADC1_DMA_IRQ_PRIORITY,

+                                 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

+                                 (void *)adcp);

+      osalDbgAssert(!b, "stream already allocated");

       dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);

       rccEnableADC1(FALSE);

     }

@@ -409,11 +404,11 @@ void adc_lld_start(ADCDriver *adcp) {
 

 #if STM32_ADC_USE_SDADC1

     if (&SDADCD1 == adcp) {

-      bool_t b = dmaStreamAllocate(adcp->dmastp,

-                                   STM32_ADC_SDADC1_DMA_IRQ_PRIORITY,

-                                   (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

-                                   (void *)adcp);

-      chDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");

+      bool b = dmaStreamAllocate(adcp->dmastp,

+                                 STM32_ADC_SDADC1_DMA_IRQ_PRIORITY,

+                                 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

+                                 (void *)adcp);

+      osalDbgAssert(!b, "stream already allocated");

       dmaStreamSetPeripheral(adcp->dmastp, &SDADC1->JDATAR);

       rccEnableSDADC1(FALSE);

       PWR->CR |= PWR_CR_SDADC1EN;

@@ -426,11 +421,11 @@ void adc_lld_start(ADCDriver *adcp) {
 

 #if STM32_ADC_USE_SDADC2

     if (&SDADCD2 == adcp) {

-      bool_t b = dmaStreamAllocate(adcp->dmastp,

-                                   STM32_ADC_SDADC2_DMA_IRQ_PRIORITY,

-                                   (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

-                                   (void *)adcp);

-      chDbgAssert(!b, "adc_lld_start(), #3", "stream already allocated");

+      bool b = dmaStreamAllocate(adcp->dmastp,

+                                 STM32_ADC_SDADC2_DMA_IRQ_PRIORITY,

+                                 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

+                                 (void *)adcp);

+      osalDbgAssert(!b, "stream already allocated");

       dmaStreamSetPeripheral(adcp->dmastp, &SDADC2->JDATAR);

       rccEnableSDADC1(FALSE);

       PWR->CR |= PWR_CR_SDADC2EN;

@@ -443,11 +438,11 @@ void adc_lld_start(ADCDriver *adcp) {
 

 #if STM32_ADC_USE_SDADC3

     if (&SDADCD3 == adcp) {

-      bool_t b = dmaStreamAllocate(adcp->dmastp,

-                                   STM32_ADC_SDADC3_DMA_IRQ_PRIORITY,

-                                   (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

-                                   (void *)adcp);

-      chDbgAssert(!b, "adc_lld_start(), #4", "stream already allocated");

+      bool b = dmaStreamAllocate(adcp->dmastp,

+                                 STM32_ADC_SDADC3_DMA_IRQ_PRIORITY,

+                                 (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,

+                                 (void *)adcp);

+      osalDbgAssert(!b, "stream already allocated");

       dmaStreamSetPeripheral(adcp->dmastp, &SDADC3->JDATAR);

       rccEnableSDADC1(FALSE);

       PWR->CR |= PWR_CR_SDADC3EN;

@@ -598,7 +593,7 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
 #endif /* STM32_ADC_USE_SDADC */

 #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC

   else {

-    chDbgAssert(FALSE, "adc_lld_start_conversion(), #1", "invalid state");

+    osalDbgAssert(FALSE, "invalid state");

   }

 #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */

 }

@@ -632,10 +627,10 @@ void adc_lld_stop_conversion(ADCDriver *adcp) {
  */

 void adcSTM32Calibrate(ADCDriver *adcp) {

 

-  chDbgAssert((adcp->state == ADC_READY) ||

+  osalDbgAssert((adcp->state == ADC_READY) ||

               (adcp->state == ADC_COMPLETE) ||

               (adcp->state == ADC_ERROR),

-              "adcSTM32Calibrate(), #1", "not ready");

+              "not ready");

 

 #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC

   if (adcp->adc != NULL)

@@ -673,7 +668,7 @@ void adcSTM32Calibrate(ADCDriver *adcp) {
 #endif /* STM32_ADC_USE_SDADC */

 #if STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC

   else {

-    chDbgAssert(FALSE, "adcSTM32Calibrate(), #2", "invalid state");

+    osalDbgAssert(FALSE, "invalid state");

   }

 #endif /* STM32_ADC_USE_ADC && STM32_ADC_USE_SDADC */

 }

diff --git a/os/hal/ports/STM32F37x/ext_lld_isr.c b/os/hal/ports/STM32F37x/ext_lld_isr.c
index f43f3aecb..642f6f8c4 100644
--- a/os/hal/ports/STM32F37x/ext_lld_isr.c
+++ b/os/hal/ports/STM32F37x/ext_lld_isr.c
@@ -22,7 +22,6 @@
  * @{

  */

 

-#include "ch.h"

 #include "hal.h"

 

 #if HAL_USE_EXT || defined(__DOXYGEN__)

@@ -55,14 +54,14 @@
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector58) {

+OSAL_IRQ_HANDLER(Vector58) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   EXTI->PR = (1 << 0);

   EXTD1.config->channels[0].cb(&EXTD1, 0);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -72,14 +71,14 @@ CH_IRQ_HANDLER(Vector58) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector5C) {

+OSAL_IRQ_HANDLER(Vector5C) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   EXTI->PR = (1 << 1);

   EXTD1.config->channels[1].cb(&EXTD1, 1);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -89,14 +88,14 @@ CH_IRQ_HANDLER(Vector5C) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector60) {

+OSAL_IRQ_HANDLER(Vector60) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   EXTI->PR = (1 << 2);

   EXTD1.config->channels[2].cb(&EXTD1, 2);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -106,14 +105,14 @@ CH_IRQ_HANDLER(Vector60) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector64) {

+OSAL_IRQ_HANDLER(Vector64) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   EXTI->PR = (1 << 3);

   EXTD1.config->channels[3].cb(&EXTD1, 3);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -123,14 +122,14 @@ CH_IRQ_HANDLER(Vector64) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector68) {

+OSAL_IRQ_HANDLER(Vector68) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   EXTI->PR = (1 << 4);

   EXTD1.config->channels[4].cb(&EXTD1, 4);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -140,10 +139,10 @@ CH_IRQ_HANDLER(Vector68) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector9C) {

+OSAL_IRQ_HANDLER(Vector9C) {

   uint32_t pr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));

   EXTI->PR = pr;

@@ -158,7 +157,7 @@ CH_IRQ_HANDLER(Vector9C) {
   if (pr & (1 << 9))

     EXTD1.config->channels[9].cb(&EXTD1, 9);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -168,10 +167,10 @@ CH_IRQ_HANDLER(Vector9C) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(VectorE0) {

+OSAL_IRQ_HANDLER(VectorE0) {

   uint32_t pr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |

                    (1 << 15));

@@ -189,7 +188,7 @@ CH_IRQ_HANDLER(VectorE0) {
   if (pr & (1 << 15))

     EXTD1.config->channels[15].cb(&EXTD1, 15);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -199,14 +198,14 @@ CH_IRQ_HANDLER(VectorE0) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector44) {

+OSAL_IRQ_HANDLER(Vector44) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   EXTI->PR = (1 << 16);

   EXTD1.config->channels[16].cb(&EXTD1, 16);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -216,14 +215,14 @@ CH_IRQ_HANDLER(Vector44) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(VectorE4) {

+OSAL_IRQ_HANDLER(VectorE4) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   EXTI->PR = (1 << 17);

   EXTD1.config->channels[17].cb(&EXTD1, 17);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -233,14 +232,14 @@ CH_IRQ_HANDLER(VectorE4) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(VectorE8) {

+OSAL_IRQ_HANDLER(VectorE8) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   EXTI->PR = (1 << 18);

   EXTD1.config->channels[18].cb(&EXTD1, 18);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -250,14 +249,14 @@ CH_IRQ_HANDLER(VectorE8) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector48) {

+OSAL_IRQ_HANDLER(Vector48) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   EXTI->PR = (1 << 19);

   EXTD1.config->channels[19].cb(&EXTD1, 19);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -267,14 +266,14 @@ CH_IRQ_HANDLER(Vector48) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector4C) {

+OSAL_IRQ_HANDLER(Vector4C) {

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   EXTI->PR = (1 << 20);

   EXTD1.config->channels[20].cb(&EXTD1, 20);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -284,10 +283,10 @@ CH_IRQ_HANDLER(Vector4C) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector140) {

+OSAL_IRQ_HANDLER(Vector140) {

   uint32_t pr;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   pr = EXTI->PR & ((1 << 21) | (1 << 22));

   EXTI->PR = pr;

@@ -296,7 +295,7 @@ CH_IRQ_HANDLER(Vector140) {
   if (pr & (1 << 22))

     EXTD1.config->channels[22].cb(&EXTD1, 22);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 #endif

 

@@ -311,32 +310,19 @@ CH_IRQ_HANDLER(Vector140) {
  */

 void ext_lld_exti_irq_enable(void) {

 

-  nvicEnableVector(EXTI0_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI0_IRQ_PRIORITY));

-  nvicEnableVector(EXTI1_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI1_IRQ_PRIORITY));

-  nvicEnableVector(EXTI2_TS_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI2_IRQ_PRIORITY));

-  nvicEnableVector(EXTI3_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI3_IRQ_PRIORITY));

-  nvicEnableVector(EXTI4_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI4_IRQ_PRIORITY));

-  nvicEnableVector(EXTI9_5_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI5_9_IRQ_PRIORITY));

-  nvicEnableVector(EXTI15_10_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI10_15_IRQ_PRIORITY));

-  nvicEnableVector(PVD_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI16_IRQ_PRIORITY));

-  nvicEnableVector(RTC_Alarm_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI17_IRQ_PRIORITY));

-  nvicEnableVector(USBWakeUp_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI18_IRQ_PRIORITY));

-  nvicEnableVector(TAMPER_STAMP_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI19_IRQ_PRIORITY));

-  nvicEnableVector(RTC_WKUP_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI20_IRQ_PRIORITY));

-  nvicEnableVector(COMP_IRQn,

-                   CORTEX_PRIORITY_MASK(STM32_EXT_EXTI21_22_IRQ_PRIORITY));

+  nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);

+  nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);

+  nvicEnableVector(EXTI2_TS_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);

+  nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);

+  nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);

+  nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);

+  nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);

+  nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);

+  nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);

+  nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);

+  nvicEnableVector(TAMPER_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);

+  nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);

+  nvicEnableVector(COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);

 }

 

 /**

diff --git a/os/hal/ports/STM32F37x/hal_lld.c b/os/hal/ports/STM32F37x/hal_lld.c
index a47ab59fc..6234137b0 100644
--- a/os/hal/ports/STM32F37x/hal_lld.c
+++ b/os/hal/ports/STM32F37x/hal_lld.c
@@ -22,7 +22,6 @@
  * @{

  */

 

-#include "ch.h"

 #include "hal.h"

 

 /*===========================================================================*/

@@ -103,17 +102,6 @@ void hal_lld_init(void) {
   rccResetAPB1(0xFFFFFFFF);

   rccResetAPB2(0xFFFFFFFF);

 

-  /* SysTick initialization using the system clock.*/

-  SysTick->LOAD = STM32_HCLK / CH_FREQUENCY - 1;

-  SysTick->VAL = 0;

-  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |

-                  SysTick_CTRL_ENABLE_Msk |

-                  SysTick_CTRL_TICKINT_Msk;

-

-  /* DWT cycle counter enable.*/

-  SCS_DEMCR |= SCS_DEMCR_TRCENA;

-  DWT_CTRL  |= DWT_CTRL_CYCCNTENA;

-

   /* PWR clock enabled.*/

   rccEnablePWRInterface(FALSE);

 

diff --git a/os/hal/ports/STM32F37x/hal_lld.h b/os/hal/ports/STM32F37x/hal_lld.h
index 96659baf3..2d7a0dac1 100644
--- a/os/hal/ports/STM32F37x/hal_lld.h
+++ b/os/hal/ports/STM32F37x/hal_lld.h
@@ -1007,6 +1007,7 @@ typedef uint32_t halrtcnt_t;
 /*===========================================================================*/

 

 /* STM32 ISR, DMA and RCC helpers.*/

+#include "nvic.h"

 #include "stm32_isr.h"

 #include "stm32_dma.h"

 #include "stm32_rcc.h"

diff --git a/os/hal/ports/STM32F37x/platform.mk b/os/hal/ports/STM32F37x/platform.mk
index 1cd7f9260..fbcaaa80f 100644
--- a/os/hal/ports/STM32F37x/platform.mk
+++ b/os/hal/ports/STM32F37x/platform.mk
@@ -1,5 +1,6 @@
 # List of all the STM32F37x platform files.

-PLATFORMSRC = ${CHIBIOS}/os/hal/ports/STM32F37x/stm32_dma.c \

+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \

+              ${CHIBIOS}/os/hal/ports/STM32F37x/stm32_dma.c \

               ${CHIBIOS}/os/hal/ports/STM32F37x/hal_lld.c \

               ${CHIBIOS}/os/hal/ports/STM32F37x/adc_lld.c \

               ${CHIBIOS}/os/hal/ports/STM32F37x/ext_lld_isr.c \

@@ -12,12 +13,14 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/STM32F37x/stm32_dma.c \
               ${CHIBIOS}/os/hal/ports/STM32/TIMv1/gpt_lld.c \

               ${CHIBIOS}/os/hal/ports/STM32/TIMv1/icu_lld.c \

               ${CHIBIOS}/os/hal/ports/STM32/TIMv1/pwm_lld.c \

+              ${CHIBIOS}/os/hal/ports/STM32/TIMv1/st_lld.c \

               ${CHIBIOS}/os/hal/ports/STM32/USARTv2/serial_lld.c \

               ${CHIBIOS}/os/hal/ports/STM32/USARTv2/uart_lld.c \

               ${CHIBIOS}/os/hal/ports/STM32/USBv1/usb_lld.c

 

 # Required include directories

-PLATFORMINC = ${CHIBIOS}/os/hal/ports/STM32F37x \

+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \

+              ${CHIBIOS}/os/hal/ports/STM32F37x \

               ${CHIBIOS}/os/hal/ports/STM32 \

               ${CHIBIOS}/os/hal/ports/STM32/GPIOv2 \

               ${CHIBIOS}/os/hal/ports/STM32/I2Cv2 \

diff --git a/os/hal/ports/STM32F37x/stm32_dma.c b/os/hal/ports/STM32F37x/stm32_dma.c
index b9ce0ddfc..362348957 100644
--- a/os/hal/ports/STM32F37x/stm32_dma.c
+++ b/os/hal/ports/STM32F37x/stm32_dma.c
@@ -29,7 +29,6 @@
  * @{

  */

 

-#include "ch.h"

 #include "hal.h"

 

 /* The following macro is only defined if some driver requiring DMA services

@@ -116,17 +115,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector6C) {

+OSAL_IRQ_HANDLER(Vector6C) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;

   DMA1->IFCR = STM32_DMA_ISR_MASK << 0;

   if (dma_isr_redir[0].dma_func)

     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -134,17 +133,17 @@ CH_IRQ_HANDLER(Vector6C) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector70) {

+OSAL_IRQ_HANDLER(Vector70) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;

   DMA1->IFCR = STM32_DMA_ISR_MASK << 4;

   if (dma_isr_redir[1].dma_func)

     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -152,17 +151,17 @@ CH_IRQ_HANDLER(Vector70) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector74) {

+OSAL_IRQ_HANDLER(Vector74) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;

   DMA1->IFCR = STM32_DMA_ISR_MASK << 8;

   if (dma_isr_redir[2].dma_func)

     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -170,17 +169,17 @@ CH_IRQ_HANDLER(Vector74) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector78) {

+OSAL_IRQ_HANDLER(Vector78) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;

   DMA1->IFCR = STM32_DMA_ISR_MASK << 12;

   if (dma_isr_redir[3].dma_func)

     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -188,17 +187,17 @@ CH_IRQ_HANDLER(Vector78) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector7C) {

+OSAL_IRQ_HANDLER(Vector7C) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;

   DMA1->IFCR = STM32_DMA_ISR_MASK << 16;

   if (dma_isr_redir[4].dma_func)

     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -206,17 +205,17 @@ CH_IRQ_HANDLER(Vector7C) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector80) {

+OSAL_IRQ_HANDLER(Vector80) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;

   DMA1->IFCR = STM32_DMA_ISR_MASK << 20;

   if (dma_isr_redir[5].dma_func)

     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -224,17 +223,17 @@ CH_IRQ_HANDLER(Vector80) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector84) {

+OSAL_IRQ_HANDLER(Vector84) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;

   DMA1->IFCR = STM32_DMA_ISR_MASK << 24;

   if (dma_isr_redir[6].dma_func)

     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -242,17 +241,17 @@ CH_IRQ_HANDLER(Vector84) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector120) {

+OSAL_IRQ_HANDLER(Vector120) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;

   DMA2->IFCR = STM32_DMA_ISR_MASK << 0;

   if (dma_isr_redir[7].dma_func)

     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -260,17 +259,17 @@ CH_IRQ_HANDLER(Vector120) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector124) {

+OSAL_IRQ_HANDLER(Vector124) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;

   DMA2->IFCR = STM32_DMA_ISR_MASK << 4;

   if (dma_isr_redir[8].dma_func)

     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -278,17 +277,17 @@ CH_IRQ_HANDLER(Vector124) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector128) {

+OSAL_IRQ_HANDLER(Vector128) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;

   DMA2->IFCR = STM32_DMA_ISR_MASK << 8;

   if (dma_isr_redir[9].dma_func)

     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -296,17 +295,17 @@ CH_IRQ_HANDLER(Vector128) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector12C) {

+OSAL_IRQ_HANDLER(Vector12C) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;

   DMA2->IFCR = STM32_DMA_ISR_MASK << 12;

   if (dma_isr_redir[10].dma_func)

     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /**

@@ -314,17 +313,17 @@ CH_IRQ_HANDLER(Vector12C) {
  *

  * @isr

  */

-CH_IRQ_HANDLER(Vector130) {

+OSAL_IRQ_HANDLER(Vector130) {

   uint32_t flags;

 

-  CH_IRQ_PROLOGUE();

+  OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;

   DMA2->IFCR = STM32_DMA_ISR_MASK << 16;

   if (dma_isr_redir[11].dma_func)

     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);

 

-  CH_IRQ_EPILOGUE();

+  OSAL_IRQ_EPILOGUE();

 }

 

 /*===========================================================================*/

@@ -374,12 +373,12 @@ void dmaInit(void) {
  *

  * @special

  */

-bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,

-                         uint32_t priority,

-                         stm32_dmaisr_t func,

-                         void *param) {

+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,

+                       uint32_t priority,

+                       stm32_dmaisr_t func,

+                       void *param) {

 

-  chDbgCheck(dmastp != NULL, "dmaStreamAllocate");

+  osalDbgCheck(dmastp != NULL);

 

   /* Checks if the stream is already taken.*/

   if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)

@@ -424,11 +423,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
  */

 void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {

 

-  chDbgCheck(dmastp != NULL, "dmaStreamRelease");

+  osalDbgCheck(dmastp != NULL);

 

   /* Check if the streams is not taken.*/

-  chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,

-              "dmaStreamRelease(), #1", "not allocated");

+  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,

+                "not allocated");

 

   /* Disables the associated IRQ vector.*/

   nvicDisableVector(dmastp->vector);

diff --git a/os/hal/ports/STM32F37x/stm32_dma.h b/os/hal/ports/STM32F37x/stm32_dma.h
index 79d295598..e77b3ba77 100644
--- a/os/hal/ports/STM32F37x/stm32_dma.h
+++ b/os/hal/ports/STM32F37x/stm32_dma.h
@@ -392,10 +392,10 @@ extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
 extern "C" {

 #endif

   void dmaInit(void);

-  bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp,

-                           uint32_t priority,

-                           stm32_dmaisr_t func,

-                           void *param);

+  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,

+                         uint32_t priority,

+                         stm32_dmaisr_t func,

+                         void *param);

   void dmaStreamRelease(const stm32_dma_stream_t *dmastp);

 #ifdef __cplusplus

 }

diff --git a/os/hal/ports/STM32F37x/stm32_registry.h b/os/hal/ports/STM32F37x/stm32_registry.h
index 8f0842263..3a7cdfaf2 100644
--- a/os/hal/ports/STM32F37x/stm32_registry.h
+++ b/os/hal/ports/STM32F37x/stm32_registry.h
@@ -34,172 +34,164 @@
  * @{

  */

 /* ADC attributes.*/

-#define STM32_HAS_ADC1          TRUE

-#define STM32_ADC1_DMA_MSK      (STM32_DMA_STREAM_ID_MSK(1, 1))

-#define STM32_ADC1_DMA_CHN      0x00000000

+#define STM32_HAS_ADC1                      TRUE

+#define STM32_HAS_ADC2                      FALSE

+#define STM32_HAS_ADC3                      FALSE

+#define STM32_HAS_ADC4                      FALSE

 

-#define STM32_HAS_ADC2          FALSE

-#define STM32_ADC2_DMA_MSK      0

-#define STM32_ADC2_DMA_CHN      0x00000000

-

-#define STM32_HAS_ADC3          FALSE

-#define STM32_ADC3_DMA_MSK      0

-#define STM32_ADC3_DMA_CHN      0x00000000

-

-#define STM32_HAS_ADC4          FALSE

-#define STM32_ADC4_DMA_MSK      0

-#define STM32_ADC4_DMA_CHN      0x00000000

-

-#define STM32_HAS_SDADC1        TRUE

-#define STM32_SDADC1_DMA_MSK    (STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_SDADC1_DMA_CHN    0x00000000

-

-#define STM32_HAS_SDADC2        TRUE

-#define STM32_SDADC2_DMA_MSK    (STM32_DMA_STREAM_ID_MSK(2, 4))

-#define STM32_SDADC2_DMA_CHN    0x00000000

-

-#define STM32_HAS_SDADC3        TRUE

-#define STM32_SDADC3_DMA_MSK    (STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_SDADC3_DMA_CHN    0x00000000

+#define STM32_HAS_SDADC1                    TRUE

+#define STM32_HAS_SDADC2                    TRUE

+#define STM32_HAS_SDADC3                    TRUE

 

 /* CAN attributes.*/

-#define STM32_HAS_CAN1          TRUE

-#define STM32_HAS_CAN2          FALSE

-#define STM32_CAN_MAX_FILTERS   14

+#define STM32_HAS_CAN1                      TRUE

+#define STM32_HAS_CAN2                      FALSE

+#define STM32_CAN_MAX_FILTERS               14

 

 /* DAC attributes.*/

-#define STM32_HAS_DAC           TRUE

+#define STM32_HAS_DAC1                      TRUE

+#define STM32_HAS_DAC2                      TRUE

 

 /* DMA attributes.*/

-#define STM32_ADVANCED_DMA      FALSE

-#define STM32_HAS_DMA1          TRUE

-#define STM32_HAS_DMA2          TRUE

+#define STM32_ADVANCED_DMA                  FALSE

+#define STM32_HAS_DMA1                      TRUE

+#define STM32_HAS_DMA2                      TRUE

 

 /* ETH attributes.*/

-#define STM32_HAS_ETH           FALSE

+#define STM32_HAS_ETH                       FALSE

 

 /* EXTI attributes.*/

-#define STM32_EXTI_NUM_CHANNELS 29

+#define STM32_EXTI_NUM_CHANNELS             29

 

 /* GPIO attributes.*/

-#define STM32_HAS_GPIOA         TRUE

-#define STM32_HAS_GPIOB         TRUE

-#define STM32_HAS_GPIOC         TRUE

-#define STM32_HAS_GPIOD         TRUE

-#define STM32_HAS_GPIOE         TRUE

-#define STM32_HAS_GPIOF         TRUE

-#define STM32_HAS_GPIOG         FALSE

-#define STM32_HAS_GPIOH         FALSE

-#define STM32_HAS_GPIOI         FALSE

+#define STM32_HAS_GPIOA                     TRUE

+#define STM32_HAS_GPIOB                     TRUE

+#define STM32_HAS_GPIOC                     TRUE

+#define STM32_HAS_GPIOD                     TRUE

+#define STM32_HAS_GPIOE                     TRUE

+#define STM32_HAS_GPIOF                     TRUE

+#define STM32_HAS_GPIOG                     FALSE

+#define STM32_HAS_GPIOH                     FALSE

+#define STM32_HAS_GPIOI                     FALSE

 

 /* I2C attributes.*/

-#define STM32_HAS_I2C1          TRUE

-#define STM32_I2C1_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_I2C1_RX_DMA_CHN   0x00000000

-#define STM32_I2C1_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_I2C1_TX_DMA_CHN   0x00000000

-

-#define STM32_HAS_I2C2          TRUE

-#define STM32_I2C2_RX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_I2C2_RX_DMA_CHN   0x00000000

-#define STM32_I2C2_TX_DMA_MSK   (STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_I2C2_TX_DMA_CHN   0x00000000

-

-#define STM32_HAS_I2C3          FALSE

-#define STM32_I2C3_RX_DMA_MSK   0

-#define STM32_I2C3_RX_DMA_CHN   0x00000000

-#define STM32_I2C3_TX_DMA_MSK   0

-#define STM32_I2C3_TX_DMA_CHN   0x00000000

+#define STM32_HAS_I2C1                      TRUE

+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)

+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)

+

+#define STM32_HAS_I2C2                      TRUE

+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

+

+#define STM32_HAS_I2C3                      FALSE

 

 /* RTC attributes.*/

-#define STM32_HAS_RTC           TRUE

-#define STM32_RTC_HAS_SUBSECONDS TRUE

-#define STM32_RTC_IS_CALENDAR   TRUE

+#define STM32_HAS_RTC                       TRUE

+#define STM32_RTC_HAS_SUBSECONDS            TRUE

+#define STM32_RTC_IS_CALENDAR               TRUE

 

 /* SDIO attributes.*/

-#define STM32_HAS_SDIO          FALSE

+#define STM32_HAS_SDIO                      FALSE

 

 /* SPI attributes.*/

-#define STM32_HAS_SPI1          TRUE

-#define STM32_SPI1_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 2)

-#define STM32_SPI1_RX_DMA_CHN   0x00000000

-#define STM32_SPI1_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 3)

-#define STM32_SPI1_TX_DMA_CHN   0x00000000

-

-#define STM32_HAS_SPI2          TRUE

-#define STM32_SPI2_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 4)

-#define STM32_SPI2_RX_DMA_CHN   0x00000000

-#define STM32_SPI2_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(1, 5)

-#define STM32_SPI2_TX_DMA_CHN   0x00000000

-

-#define STM32_HAS_SPI3          TRUE

-#define STM32_SPI3_RX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 1)

-#define STM32_SPI3_RX_DMA_CHN   0x00000000

-#define STM32_SPI3_TX_DMA_MSK   STM32_DMA_STREAM_ID_MSK(2, 2)

-#define STM32_SPI3_TX_DMA_CHN   0x00000000

+#define STM32_HAS_SPI1                      TRUE

+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)

+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)

+

+#define STM32_HAS_SPI2                      TRUE

+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)

+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)

+

+#define STM32_HAS_SPI3                      TRUE

+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)

+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)

 

 /* TIM attributes.*/

-#define STM32_HAS_TIM1          FALSE

-#define STM32_HAS_TIM2          TRUE

-#define STM32_HAS_TIM3          TRUE

-#define STM32_HAS_TIM4          TRUE

-#define STM32_HAS_TIM5          TRUE

-#define STM32_HAS_TIM6          TRUE

-#define STM32_HAS_TIM7          TRUE

-#define STM32_HAS_TIM8          FALSE

-#define STM32_HAS_TIM9          FALSE

-#define STM32_HAS_TIM10         FALSE

-#define STM32_HAS_TIM11         FALSE

-#define STM32_HAS_TIM12         TRUE

-#define STM32_HAS_TIM13         TRUE

-#define STM32_HAS_TIM14         TRUE

-#define STM32_HAS_TIM15         TRUE

-#define STM32_HAS_TIM16         TRUE

-#define STM32_HAS_TIM17         TRUE

-#define STM32_HAS_TIM18         TRUE

-#define STM32_HAS_TIM19         TRUE

+#define STM32_TIM_MAX_CHANNELS              4

+

+#define STM32_HAS_TIM2                      TRUE

+#define STM32_TIM2_IS_32BITS                TRUE

+#define STM32_TIM2_CHANNELS                 4

+

+#define STM32_HAS_TIM3                      TRUE

+#define STM32_TIM3_IS_32BITS                FALSE

+#define STM32_TIM3_CHANNELS                 4

+

+#define STM32_HAS_TIM4                      TRUE

+#define STM32_TIM4_IS_32BITS                FALSE

+#define STM32_TIM4_CHANNELS                 4

+

+#define STM32_HAS_TIM5                      TRUE

+#define STM32_TIM5_IS_32BITS                TRUE

+#define STM32_TIM5_CHANNELS                 4

+

+#define STM32_HAS_TIM6                      TRUE

+#define STM32_TIM6_IS_32BITS                FALSE

+#define STM32_TIM6_CHANNELS                 0

+

+#define STM32_HAS_TIM7                      TRUE

+#define STM32_TIM7_IS_32BITS                FALSE

+#define STM32_TIM7_CHANNELS                 0

+

+#define STM32_HAS_TIM12                     TRUE

+#define STM32_TIM12_IS_32BITS               FALSE

+#define STM32_TIM12_CHANNELS                2

+

+#define STM32_HAS_TIM13                     TRUE

+#define STM32_TIM13_IS_32BITS               FALSE

+#define STM32_TIM13_CHANNELS                2

+

+#define STM32_HAS_TIM14                     TRUE

+#define STM32_TIM14_IS_32BITS               FALSE

+#define STM32_TIM14_CHANNELS                2

+

+#define STM32_HAS_TIM15                     TRUE

+#define STM32_TIM15_IS_32BITS               FALSE

+#define STM32_TIM15_CHANNELS                2

+

+#define STM32_HAS_TIM16                     TRUE

+#define STM32_TIM16_IS_32BITS               FALSE

+#define STM32_TIM16_CHANNELS                2

+

+#define STM32_HAS_TIM17                     TRUE

+#define STM32_TIM17_IS_32BITS               FALSE

+#define STM32_TIM17_CHANNELS                2

+

+#define STM32_HAS_TIM18                     TRUE

+#define STM32_TIM18_IS_32BITS               FALSE

+#define STM32_TIM18_CHANNELS                0

+

+#define STM32_HAS_TIM19                     TRUE

+#define STM32_TIM19_IS_32BITS               FALSE

+#define STM32_TIM19_CHANNELS                4

+

+#define STM32_HAS_TIM1                      FALSE

+#define STM32_HAS_TIM8                      FALSE

+#define STM32_HAS_TIM9                      FALSE

+#define STM32_HAS_TIM10                     FALSE

+#define STM32_HAS_TIM11                     FALSE

 

 /* USART attributes.*/

-#define STM32_HAS_USART1        TRUE

-#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))

-#define STM32_USART1_RX_DMA_CHN 0x00000000

-#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))

-#define STM32_USART1_TX_DMA_CHN 0x00000000

-

-#define STM32_HAS_USART2        TRUE

-#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))

-#define STM32_USART2_RX_DMA_CHN 0x00000000

-#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))

-#define STM32_USART2_TX_DMA_CHN 0x00000000

-

-#define STM32_HAS_USART3        TRUE

-#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))

-#define STM32_USART3_RX_DMA_CHN 0x00000000

-#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))

-#define STM32_USART3_TX_DMA_CHN 0x00000000

-

-#define STM32_HAS_UART4         FALSE

-#define STM32_UART4_RX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 3))

-#define STM32_UART4_RX_DMA_CHN  0x00000000

-#define STM32_UART4_TX_DMA_MSK  (STM32_DMA_STREAM_ID_MSK(2, 5))

-#define STM32_UART4_TX_DMA_CHN  0x00000000

-

-#define STM32_HAS_UART5         FALSE

-#define STM32_UART5_RX_DMA_MSK  0

-#define STM32_UART5_RX_DMA_CHN  0x00000000

-#define STM32_UART5_TX_DMA_MSK  0

-#define STM32_UART5_TX_DMA_CHN  0x00000000

-

-#define STM32_HAS_USART6        FALSE

-#define STM32_USART6_RX_DMA_MSK 0

-#define STM32_USART6_RX_DMA_CHN 0x00000000

-#define STM32_USART6_TX_DMA_MSK 0

-#define STM32_USART6_TX_DMA_CHN 0x00000000

+#define STM32_HAS_USART1                    TRUE

+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)

+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)

+

+#define STM32_HAS_USART2                    TRUE

+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)

+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)

+

+#define STM32_HAS_USART3                    TRUE

+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)

+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)

+

+#define STM32_HAS_UART4                     FALSE

+#define STM32_HAS_UART5                     FALSE

+#define STM32_HAS_USART6                    FALSE

 

 /* USB attributes.*/

-#define STM32_HAS_USB           TRUE

-#define STM32_HAS_OTG1          FALSE

-#define STM32_HAS_OTG2          FALSE

+#define STM32_HAS_USB                       TRUE

+#define STM32_HAS_OTG1                      FALSE

+#define STM32_HAS_OTG2                      FALSE

 /** @} */

 

 #endif /* _STM32_REGISTRY_H_ */