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| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-12-03 15:17:11 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2013-12-03 15:17:11 +0000 |
| commit | 296b71cd22f32a6e2bd5910da1bfc7867fbb8e36 (patch) | |
| tree | cab8b3ee494e5714e79e0dee0c32ac34a6754eb4 /os/hal/ports/STM32F1xx | |
| parent | 130e3be57409f06dd395ef8626bf848097ea1b79 (diff) | |
| download | ChibiOS-296b71cd22f32a6e2bd5910da1bfc7867fbb8e36.tar.gz ChibiOS-296b71cd22f32a6e2bd5910da1bfc7867fbb8e36.tar.bz2 ChibiOS-296b71cd22f32a6e2bd5910da1bfc7867fbb8e36.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6534 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32F1xx')
| -rw-r--r-- | os/hal/ports/STM32F1xx/stm32_registry.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/os/hal/ports/STM32F1xx/stm32_registry.h b/os/hal/ports/STM32F1xx/stm32_registry.h index d03894d40..46ce6e297 100644 --- a/os/hal/ports/STM32F1xx/stm32_registry.h +++ b/os/hal/ports/STM32F1xx/stm32_registry.h @@ -98,6 +98,9 @@ #define STM32_HAS_SPI2 FALSE
#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 4
@@ -242,6 +245,9 @@ #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 4
@@ -386,6 +392,9 @@ #define STM32_HAS_SPI2 FALSE
#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 4
@@ -515,6 +524,9 @@ #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 4
@@ -653,6 +665,10 @@ #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 4
@@ -823,6 +839,10 @@ #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 4
@@ -993,6 +1013,10 @@ #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
/* TIM attributes.*/
#define STM32_TIM_MAX_CHANNELS 4
|