Fixed bug #439.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6461 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 14 insertions, 14 deletions

diff --git a/os/hal/ports/STM32F1xx/stm32_dma.c b/os/hal/ports/STM32F1xx/stm32_dma.c
index f8cee45ad..c3b39d37c 100644
--- a/os/hal/ports/STM32F1xx/stm32_dma.c
+++ b/os/hal/ports/STM32F1xx/stm32_dma.c
@@ -128,7 +128,7 @@ OSAL_IRQ_HANDLER(Vector6C) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = STM32_DMA_ISR_MASK << 0;

+  DMA1->IFCR = flags << 0;

   if (dma_isr_redir[0].dma_func)

     dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);

 

@@ -146,7 +146,7 @@ OSAL_IRQ_HANDLER(Vector70) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = STM32_DMA_ISR_MASK << 4;

+  DMA1->IFCR = flags << 4;

   if (dma_isr_redir[1].dma_func)

     dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);

 

@@ -164,7 +164,7 @@ OSAL_IRQ_HANDLER(Vector74) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = STM32_DMA_ISR_MASK << 8;

+  DMA1->IFCR = flags << 8;

   if (dma_isr_redir[2].dma_func)

     dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);

 

@@ -182,7 +182,7 @@ OSAL_IRQ_HANDLER(Vector78) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = STM32_DMA_ISR_MASK << 12;

+  DMA1->IFCR = flags << 12;

   if (dma_isr_redir[3].dma_func)

     dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);

 

@@ -200,7 +200,7 @@ OSAL_IRQ_HANDLER(Vector7C) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = STM32_DMA_ISR_MASK << 16;

+  DMA1->IFCR = flags << 16;

   if (dma_isr_redir[4].dma_func)

     dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);

 

@@ -218,7 +218,7 @@ OSAL_IRQ_HANDLER(Vector80) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = STM32_DMA_ISR_MASK << 20;

+  DMA1->IFCR = flags << 20;

   if (dma_isr_redir[5].dma_func)

     dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);

 

@@ -236,7 +236,7 @@ OSAL_IRQ_HANDLER(Vector84) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = STM32_DMA_ISR_MASK << 24;

+  DMA1->IFCR = flags << 24;

   if (dma_isr_redir[6].dma_func)

     dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);

 

@@ -255,7 +255,7 @@ OSAL_IRQ_HANDLER(Vector120) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;

-  DMA2->IFCR = STM32_DMA_ISR_MASK << 0;

+  DMA2->IFCR = flags << 0;

   if (dma_isr_redir[7].dma_func)

     dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);

 

@@ -273,7 +273,7 @@ OSAL_IRQ_HANDLER(Vector124) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;

-  DMA2->IFCR = STM32_DMA_ISR_MASK << 4;

+  DMA2->IFCR = flags << 4;

   if (dma_isr_redir[8].dma_func)

     dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);

 

@@ -291,7 +291,7 @@ OSAL_IRQ_HANDLER(Vector128) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;

-  DMA2->IFCR = STM32_DMA_ISR_MASK << 8;

+  DMA2->IFCR = flags << 8;

   if (dma_isr_redir[9].dma_func)

     dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);

 

@@ -310,7 +310,7 @@ OSAL_IRQ_HANDLER(Vector12C) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;

-  DMA2->IFCR = STM32_DMA_ISR_MASK << 12;

+  DMA2->IFCR = flags << 12;

   if (dma_isr_redir[10].dma_func)

     dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);

 

@@ -328,7 +328,7 @@ OSAL_IRQ_HANDLER(Vector130) {
   OSAL_IRQ_PROLOGUE();

 

   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;

-  DMA2->IFCR = STM32_DMA_ISR_MASK << 16;

+  DMA2->IFCR = flags << 16;

   if (dma_isr_redir[11].dma_func)

     dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);

 

@@ -350,7 +350,7 @@ OSAL_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
   /* Check on channel 4.*/

   flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;

   if (flags & STM32_DMA_ISR_MASK) {

-    DMA2->IFCR = STM32_DMA_ISR_MASK << 12;

+    DMA2->IFCR = flags << 12;

     if (dma_isr_redir[10].dma_func)

       dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);

   }

@@ -358,7 +358,7 @@ OSAL_IRQ_HANDLER(DMA2_Ch4_5_IRQHandler) {
   /* Check on channel 5.*/

   flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;

   if (flags & STM32_DMA_ISR_MASK) {

-    DMA2->IFCR = STM32_DMA_ISR_MASK << 16;

+    DMA2->IFCR = flags << 16;

     if (dma_isr_redir[11].dma_func)

       dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);

   }