git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9480 35acf78f-673a-0410-8e92-d51de3d6d3f4

3 files changed, 66 insertions, 16 deletions

diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c
index 4f4036a15..d395e0b43 100644
--- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c
+++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.c
@@ -123,21 +123,29 @@ void qspi_lld_init(void) {
  */

 void qspi_lld_start(QSPIDriver *qspip) {

 

-  /* If in stopped state then enables the QUADSPI and DMA clocks.*/

+  /* If in stopped state then full initialization.*/

   if (qspip->state == QSPI_STOP) {

 #if STM32_QSPI_USE_QUADSPI1

     if (&QSPID1 == qspip) {

-      rccEnableQUADSPI1(FALSE);

+      bool b = dmaStreamAllocate(qspip->dma,

+                                 STM32_QSPI_QUADSPI1_IRQ_PRIORITY,

+                                 (stm32_dmaisr_t)qspi_lld_serve_dma_interrupt,

+                                 (void *)qspip);

+      osalDbgAssert(!b, "stream already allocated");

+      rccEnableQUADSPI1(false);

     }

 #endif

+

+    /* Common initializations.*/

+    dmaStreamSetPeripheral(qspip->dma, &qspip->qspi->DR);

   }

 

   /* QSPI setup and enable.*/

-//  spip->spi->CR1  = 0;

-//  spip->spi->CR1  = spip->config->cr1 | SPI_CR1_MSTR;

-//  spip->spi->CR2  = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE |

-//                    SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN;

-//  spip->spi->CR1 |= SPI_CR1_SPE;

+  qspip->qspi->CR  = ((STM32_QSPI_QUADSPI1_PRESCALER_VALUE - 1U) << 24U) |

+                      QUADSPI_CR_TCIE | QUADSPI_CR_TEIE | QUADSPI_CR_DMAEN |

+                      QUADSPI_CR_EN;

+  qspip->qspi->FCR = QUADSPI_FCR_CTEF | QUADSPI_FCR_CTCF |

+                     QUADSPI_FCR_CSMF | QUADSPI_FCR_CTOF;

 }

 

 /**

@@ -153,10 +161,12 @@ void qspi_lld_stop(QSPIDriver *qspip) {
   if (qspip->state == QSPI_READY) {

 

     /* QSPI disable.*/

-//    spip->spi->CR1 = 0;

-//    spip->spi->CR2 = 0;

+    qspip->qspi->CR = 0U;

+

+    /* Releasing the DMA.*/

     dmaStreamRelease(qspip->dma);

 

+    /* Stopping involved clocks.*/

 #if STM32_QSPI_USE_QUADSPI1

     if (&QSPID1 == qspip) {

       rccDisableQUADSPI1(FALSE);

@@ -166,13 +176,32 @@ void qspi_lld_stop(QSPIDriver *qspip) {
 }

 

 /**

- * @brief   Sends data over the QSPI bus.

- * @details This asynchronous function starts a transmit operation.

+ * @brief   Sends a command without data phase.

  * @post    At the end of the operation the configured callback is invoked.

  *

  * @param[in] qspip     pointer to the @p QSPIDriver object

  * @param[in] cmd       pointer to the command descriptor

- * @param[in] n         number of words to send

+ *

+ * @notapi

+ */

+void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp) {

+

+  qspip->qspi->CCR = cmdp->cfg;

+  if ((cmdp->cfg & QSPI_CFG_ALT_MODE_MASK) != QSPI_CFG_ALT_MODE_NONE) {

+    qspip->qspi->ABR = cmdp->alt;

+  }

+  if ((cmdp->cfg & QSPI_CFG_ADDR_MODE_MASK) != QSPI_CFG_ADDR_MODE_NONE) {

+    qspip->qspi->AR  = cmdp->addr;

+  }

+}

+

+/**

+ * @brief   Sends a command with data over the QSPI bus.

+ * @post    At the end of the operation the configured callback is invoked.

+ *

+ * @param[in] qspip     pointer to the @p QSPIDriver object

+ * @param[in] cmd       pointer to the command descriptor

+ * @param[in] n         number of bytes to send

  * @param[in] txbuf     the pointer to the transmit buffer

  *

  * @notapi

@@ -184,17 +213,21 @@ void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,
   dmaStreamSetTransactionSize(qspip->dma, n);

   dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_M2P);

 

+  qspip->qspi->DLR = n - 1;

+  qspip->qspi->ABR = cmdp->alt;

+  qspip->qspi->CCR = cmdp->cfg;

+  qspip->qspi->AR  = cmdp->addr;

+

   dmaStreamEnable(qspip->dma);

 }

 

 /**

- * @brief   Receives data from the QSPI bus.

- * @details This asynchronous function starts a receive operation.

+ * @brief   Sends a command then receives data over the QSPI bus.

  * @post    At the end of the operation the configured callback is invoked.

  *

  * @param[in] qspip     pointer to the @p QSPIDriver object

  * @param[in] cmd       pointer to the command descriptor

- * @param[in] n         number of words to receive

+ * @param[in] n         number of bytes to send

  * @param[out] rxbuf    the pointer to the receive buffer

  *

  * @notapi

@@ -206,6 +239,11 @@ void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,
   dmaStreamSetTransactionSize(qspip->dma, n);

   dmaStreamSetMode(qspip->dma, qspip->dmamode | STM32_DMA_CR_DIR_P2M);

 

+  qspip->qspi->DLR = n - 1;

+  qspip->qspi->ABR = cmdp->alt;

+  qspip->qspi->CCR = cmdp->cfg | QUADSPI_CCR_FMODE_0;

+  qspip->qspi->AR  = cmdp->addr;

+

   dmaStreamEnable(qspip->dma);

 }

 

diff --git a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h
index 14dc01b2f..100572dfc 100644
--- a/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h
+++ b/os/hal/ports/STM32/LLD/QUADSPIv1/hal_qspi_lld.h
@@ -49,6 +49,16 @@
 #endif

 

 /**

+ * @brief   QUADSPI1 prescaler setting.

+ * @note    This is the prescaler divider value 1..256. The maximum frequency

+ *          varies depending on the STM32 model and operating conditions,

+ *          find the details in the data sheet.

+ */

+#if !defined(STM32_QSPI_QUADSPI1_PRESCALER_VALUE) || defined(__DOXYGEN__)

+#define STM32_QSPI_QUADSPI1_PRESCALER_VALUE 4

+#endif

+

+/**

  * @brief   QUADSPI1 interrupt priority level setting.

  */

 #if !defined(STM32_QSPI_QUADSPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)

@@ -199,6 +209,7 @@ extern "C" {
   void qspi_lld_init(void);

   void qspi_lld_start(QSPIDriver *qspip);

   void qspi_lld_stop(QSPIDriver *qspip);

+  void qspi_lld_command(QSPIDriver *qspip, const qspi_command_t *cmdp);

   void qspi_lld_send(QSPIDriver *qspip, const qspi_command_t *cmdp,

                      size_t n, const uint8_t *txbuf);

   void qspi_lld_receive(QSPIDriver *qspip, const qspi_command_t *cmdp,

diff --git a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
index a1474a5c4..09de989ca 100644
--- a/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32L4xx/stm32_registry.h
@@ -211,7 +211,8 @@
 

 /* QUADSPI attributes.*/

 #define STM32_HAS_QUADSPI1                  TRUE

-#define STM32_QUADSPI1_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(2, 7))

+#define STM32_QUADSPI1_DMA_MSK              (STM32_DMA_STREAM_ID_MSK(1, 5) |\

+                                             STM32_DMA_STREAM_ID_MSK(2, 7))

 #define STM32_QUADSPI1_DMA_CHN              0x03000000

 

 /* RTC attributes.*/