git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9712 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 25 insertions, 11 deletions

diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
index c4916b8af..73d229c78 100644
--- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c
@@ -218,12 +218,11 @@ void stm32_clock_init(void) {
     ;                                       /* Wait until LSE is stable.    */

 #endif

 

-#if STM32_MSIPLL_ENABLED

-  /* MSI PLL activation.*/

-  RCC->CR |= RCC_CR_MSIPLLEN;

-#endif

+  /* Flash setup for selected MSI speed setting.*/

+  FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |

+               STM32_MSI_FLASHBITS;

 

-  /* Changing MSIRANGE value. Meanwhile range is set by MSISRANGE which is 4MHz.*/

+  /* Changing MSIRANGE to configured value.*/

   RCC->CR |= STM32_MSIRANGE;

 

   /* Switching from MSISRANGE to MSIRANGE.*/

@@ -231,7 +230,16 @@ void stm32_clock_init(void) {
   while ((RCC->CR & RCC_CR_MSIRDY) == 0)

     ;

 

-  /* Updating MSISRANGE value. MSISRANGE can be set only when MSIRGSEL is high. 

+  /* MSI is configured SYSCLK source so wait for it to be stable as well.*/

+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI)

+    ;

+

+#if STM32_MSIPLL_ENABLED

+  /* MSI PLL (to LSE) activation */

+  RCC->CR |= RCC_CR_MSIPLLEN;

+#endif

+

+  /* Updating MSISRANGE value. MSISRANGE can be set only when MSIRGSEL is high.

      This range is used exiting the Standby mode until MSIRGSEL is set.*/

   RCC->CSR |= STM32_MSISRANGE;

 

@@ -251,7 +259,7 @@ void stm32_clock_init(void) {
   /* Waiting for PLL lock.*/

   while ((RCC->CR & RCC_CR_PLLRDY) == 0)

     ;

-#endif /* STM32_OVERDRIVE_REQUIRED */

+#endif

 

 #if STM32_ACTIVATE_PLLSAI1

   /* PLLSAI1 activation.*/

@@ -299,16 +307,22 @@ void stm32_clock_init(void) {
     RCC->CCIPR = ccipr;

   }

 

-  /* Flash setup.*/

-  FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN |

-               STM32_FLASHBITS;

+  /* Set flash WS's for SYSCLK source */

+  if (STM32_FLASHBITS > STM32_MSI_FLASHBITS)

+    FLASH->ACR = STM32_FLASHBITS;

 

-  /* Switching to the configured clock source if it is different from MSI.*/

+  /* Switching to the configured SYSCLK source if it is different from MSI.*/

 #if (STM32_SW != STM32_SW_MSI)

   RCC->CFGR |= STM32_SW;        /* Switches on the selected clock source.   */

+  /* Wait until SYSCLK is stable.*/

   while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))

     ;

 #endif

+

+  /* Reduce the flash WS's for SYSCLK source if they are less than MSI WSs */

+  if (STM32_FLASHBITS < STM32_MSI_FLASHBITS)

+    FLASH->ACR = STM32_FLASHBITS;

+

 #endif /* STM32_NO_INIT */

 

   /* SYSCFG clock enabled here because it is a multi-functional unit shared