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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-11-13 15:42:33 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-11-13 15:42:33 +0000 |
| commit | 4016e0a368ba94a66874b3f0272a4739967e5404 (patch) | |
| tree | 0b848e39e583ccaccd9a956eef72acbe1369cf72 /os/hal/ports/STM32/STM32L4xx/hal_lld.c | |
| parent | a4d9054506f3d1fedfd7d8436e12bb45ae8e6e3e (diff) | |
| download | ChibiOS-4016e0a368ba94a66874b3f0272a4739967e5404.tar.gz ChibiOS-4016e0a368ba94a66874b3f0272a4739967e5404.tar.bz2 ChibiOS-4016e0a368ba94a66874b3f0272a4739967e5404.zip | |
Added MSI PLL support to L4.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8483 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L4xx/hal_lld.c')
| -rw-r--r-- | os/hal/ports/STM32/STM32L4xx/hal_lld.c | 45 |
1 files changed, 25 insertions, 20 deletions
diff --git a/os/hal/ports/STM32/STM32L4xx/hal_lld.c b/os/hal/ports/STM32/STM32L4xx/hal_lld.c index f48cd8454..6ca9264d9 100644 --- a/os/hal/ports/STM32/STM32L4xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L4xx/hal_lld.c @@ -53,9 +53,6 @@ uint32_t SystemCoreClock = STM32_HCLK; */
static void hal_lld_backup_domain_init(void) {
- /* Backup domain access enabled and left open.*/
- PWR->CR1 |= PWR_CR1_DBP;
-
/* Reset BKP domain if different clock source selected.*/
if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) {
/* Backup domain reset.*/
@@ -63,19 +60,6 @@ static void hal_lld_backup_domain_init(void) { RCC->BDCR = 0;
}
- /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
-#if defined(STM32_LSE_BYPASS)
- /* LSE Bypass.*/
- RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
-#else
- /* No LSE Bypass.*/
- RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
-#endif
- while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
- ; /* Wait until LSE is stable. */
-#endif
-
#if HAL_USE_RTC
/* If the backup domain hasn't been initialized yet then proceed with
initialization.*/
@@ -184,12 +168,33 @@ void stm32_clock_init(void) { ; /* Wait until LSI is stable. */
#endif
+ /* Backup domain access enabled and left open.*/
+ PWR->CR1 |= PWR_CR1_DBP;
+
+#if STM32_LSE_ENABLED
+ /* LSE activation.*/
+#if defined(STM32_LSE_BYPASS)
+ /* LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+ /* No LSE Bypass.*/
+ RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+ while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+ ; /* Wait until LSE is stable. */
+#endif
+
+#if STM32_MSIPLL_ENABLED
+ /* MSI PLL activation.*/
+ RCC->CR |= RCC_CR_MSIPLLEN;
+#endif
+
#if STM32_ACTIVATE_PLL || STM32_ACTIVATE_PLLSAI1 || STM32_ACTIVATE_PLLSAI2
/* PLLM and PLLSRC are common to all PLLs.*/
- RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
- STM32_PLLQ | STM32_PLLQEN |
- STM32_PLLP | STM32_PLLPEN |
- STM32_PLLN | STM32_PLLM |
+ RCC->PLLCFGR = STM32_PLLR | STM32_PLLREN |
+ STM32_PLLQ | STM32_PLLQEN |
+ STM32_PLLP | STM32_PLLPEN |
+ STM32_PLLN | STM32_PLLM |
STM32_PLLSRC;
#endif
|