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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-27 12:01:51 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-08-27 12:01:51 +0000 |
| commit | 40af275be262e19419af9d32bc68f811c8388e2b (patch) | |
| tree | af814bb367cf302051e1b4e867d18cabcf0d81bd /os/hal/ports/STM32/STM32L1xx/stm32_rcc.h | |
| parent | e4df1ff09dbf2f53accb9f93eacc4c9db15a4c6f (diff) | |
| download | ChibiOS-40af275be262e19419af9d32bc68f811c8388e2b.tar.gz ChibiOS-40af275be262e19419af9d32bc68f811c8388e2b.tar.bz2 ChibiOS-40af275be262e19419af9d32bc68f811c8388e2b.zip | |
Fixed bug #636.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8248 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L1xx/stm32_rcc.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32L1xx/stm32_rcc.h | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h index 883712ea2..b1832a7ac 100644 --- a/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L1xx/stm32_rcc.h @@ -509,6 +509,81 @@ #define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
/**
+ * @brief Enables the TIM5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp)
+
+/**
+ * @brief Disables the TIM5 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp)
+
+/**
+ * @brief Resets the TIM5 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST)
+
+/**
+ * @brief Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Disables the TIM6 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+
+/**
+ * @brief Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
+/**
* @brief Enables the TIM9 peripheral clock.
* @note The @p lp parameter is ignored in this family.
*
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