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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-17 14:55:12 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-17 14:55:12 +0000 |
| commit | c953aa5ac86e4f913c41333a773a0903e0860d35 (patch) | |
| tree | d2c00d4f0eaf25892e5d4f4ade85b2866e2c38de /os/hal/ports/STM32/STM32L0xx | |
| parent | df330879bb5c5630e847e2e9eec471080b0d18a4 (diff) | |
| download | ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.tar.gz ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.tar.bz2 ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.zip | |
Defaulted all STM32 drivers to enable peripheral clocks during stop/sleep modes. Now RCC macros are able to set or clear the LP bit of a peripheral.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11300 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L0xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/hal_lld.c | 6 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_rcc.h | 12 |
2 files changed, 11 insertions, 7 deletions
diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.c b/os/hal/ports/STM32/STM32L0xx/hal_lld.c index 6ef788d7a..9779fc476 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.c @@ -156,7 +156,7 @@ void hal_lld_init(void) { rccResetAPB2(~0);
/* PWR clock enabled.*/
- rccEnablePWRInterface(FALSE);
+ rccEnablePWRInterface(true);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
@@ -266,7 +266,7 @@ void stm32_clock_init(void) { #if STM32_ACTIVATE_HSI48
/* Enabling SYSCFG clock. */
- rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, FALSE);
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
/* Configuring SYSCFG to enable VREFINT and HSI48 VREFINT buffer. */
SYSCFG->CFGR3 = STM32_VREFINT_EN | SYSCFG_CFGR3_ENREF_HSI48;
@@ -305,7 +305,7 @@ void stm32_clock_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
- rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
#endif /* STM32_NO_INIT */
}
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h index 01283be58..e53e6db67 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h @@ -63,6 +63,8 @@ RCC->APB1ENR |= (mask); \
if (lp) \
RCC->APB1SMENR |= (mask); \
+ else \
+ RCC->APB1SMENR &= ~(mask); \
}
/**
@@ -74,7 +76,6 @@ */
#define rccDisableAPB1(mask) { \
RCC->APB1ENR &= ~(mask); \
- RCC->APB1SMENR &= ~(mask); \
}
/**
@@ -101,6 +102,8 @@ RCC->APB2ENR |= (mask); \
if (lp) \
RCC->APB2SMENR |= (mask); \
+ else \
+ RCC->APB2SMENR &= ~(mask); \
}
/**
@@ -112,7 +115,6 @@ */
#define rccDisableAPB2(mask) { \
RCC->APB2ENR &= ~(mask); \
- RCC->APB2SMENR &= ~(mask); \
}
/**
@@ -139,6 +141,8 @@ RCC->AHBENR |= (mask); \
if (lp) \
RCC->AHBSMENR |= (mask); \
+ else \
+ RCC->AHBSMENR &= ~(mask); \
}
/**
@@ -150,7 +154,6 @@ */
#define rccDisableAHB(mask) { \
RCC->AHBENR &= ~(mask); \
- RCC->AHBSMENR &= ~(mask); \
}
/**
@@ -177,6 +180,8 @@ RCC->IOPENR |= (mask); \
if (lp) \
RCC->IOPSMENR |= (mask); \
+ else \
+ RCC->IOPSMENR &= ~(mask); \
}
/**
@@ -188,7 +193,6 @@ */
#define rccDisableIOP(mask) { \
RCC->IOPENR &= ~(mask); \
- RCC->IOPSMENR &= ~(mask); \
}
/**
|