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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-05-27 15:28:21 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-05-27 15:28:21 +0000 |
| commit | 0d9f42c9d9ce052f7ddf42174eafefae7516f99a (patch) | |
| tree | c138562f4a8dd294355a84a63816b1ac9021dd47 /os/hal/ports/STM32/STM32L0xx | |
| parent | dd4239960c73242b31d18571e6a66d9dd229b4cc (diff) | |
| download | ChibiOS-0d9f42c9d9ce052f7ddf42174eafefae7516f99a.tar.gz ChibiOS-0d9f42c9d9ce052f7ddf42174eafefae7516f99a.tar.bz2 ChibiOS-0d9f42c9d9ce052f7ddf42174eafefae7516f99a.zip | |
Fixed USART4/5 support on STM32L07x.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10205 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32L0xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/hal_lld.h | 10 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32L0xx/stm32_registry.h | 7 |
2 files changed, 13 insertions, 4 deletions
diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.h b/os/hal/ports/STM32/STM32L0xx/hal_lld.h index f1cbae0f3..ec88abfc0 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.h @@ -1049,6 +1049,16 @@ #endif
/**
+ * @brief USART4 frequency.
+ */
+#define STM32_UART4CLK STM32_PCLK1
+
+/**
+ * @brief USART5 frequency.
+ */
+#define STM32_UART5CLK STM32_PCLK1
+
+/**
* @brief LPUART1 frequency.
*/
#if (STM32_LPUART1SEL == STM32_LPUART1SEL_APB) || defined(__DOXYGEN__)
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h index c7f3c1dfd..27eff005c 100644 --- a/os/hal/ports/STM32/STM32L0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32L0xx/stm32_registry.h @@ -1472,9 +1472,10 @@ STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_USART2_TX_DMA_CHN 0x04004000
+#define STM32_USART3_8_HANDLER Vector78
+#define STM32_USART3_8_NUMBER 14
+
#define STM32_HAS_UART4 TRUE
-#define STM32_UART4_HANDLER Vector78
-#define STM32_UART4_NUMBER 14
#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_UART4_RX_DMA_CHN 0x00C000C0
@@ -1483,8 +1484,6 @@ #define STM32_UART4_TX_DMA_CHN 0x0C000C00
#define STM32_HAS_UART5 TRUE
-#define STM32_UART5_HANDLER Vector78
-#define STM32_UART5_NUMBER 14
#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_UART5_RX_DMA_CHN 0x00D000D0
|