Reduced complexity of preprocessor conditions regarding PLLs.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11184 35acf78f-673a-0410-8e92-d51de3d6d3f4

2 files changed, 15 insertions, 26 deletions

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
index e39f06ec2..526f1fda1 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
@@ -236,32 +236,14 @@ void stm32_clock_init(void) {
                      RCC_PLLCKSELR_DIVM1_VALUE(STM32_PLL1_DIVM_VALUE) |

                      RCC_PLLCKSELR_PLLSRC_VALUE(STM32_PLLSRC);

 

+    cfgmask = STM32_PLLCFGR_PLL3RGE | STM32_PLLCFGR_PLL3VCOSEL | RCC_PLLCFGR_PLL3FRACEN |

+              STM32_PLLCFGR_PLL2RGE | STM32_PLLCFGR_PLL2VCOSEL | RCC_PLLCFGR_PLL2FRACEN |

+              STM32_PLLCFGR_PLL1RGE | STM32_PLLCFGR_PLL1VCOSEL | RCC_PLLCFGR_PLL1FRACEN;

+

 #if STM32_PLL1_ENABLED == TRUE

+    RCC->PLL1FRACR = STM32_PLL1_FRACN;

     RCC->PLL1DIVR  = STM32_PLL1_DIVR | STM32_PLL1_DIVQ |

                      STM32_PLL1_DIVP | STM32_PLL1_DIVN;

-    RCC->PLL1FRACR = STM32_PLL1_FRACN;

-    RCC->CR       |= RCC_CR_PLL1ON;

-#endif

-

-#if STM32_PLL2_ENABLED == TRUE

-    RCC->PLL2DIVR  = STM32_PLL2_DIVR | STM32_PLL2_DIVQ |

-                     STM32_PLL2_DIVP | STM32_PLL2_DIVN;

-    RCC->PLL2FRACR = STM32_PLL2_FRACN;

-    RCC->CR       |= RCC_CR_PLL2ON;

-#endif

-

-#if STM32_PLL3_ENABLED == TRUE

-    RCC->PLL3DIVR  = STM32_PLL3_DIVR | STM32_PLL3_DIVQ |

-                     STM32_PLL3_DIVP | STM32_PLL3_DIVN;

-    RCC->PLL3FRACR = STM32_PLL3_FRACN;

-    RCC->CR       |= RCC_CR_PLL3ON;

-#endif

-

-   cfgmask = STM32_PLLCFGR_PLL3RGE | STM32_PLLCFGR_PLL3VCOSEL | RCC_PLLCFGR_PLL3FRACEN |

-             STM32_PLLCFGR_PLL2RGE | STM32_PLLCFGR_PLL2VCOSEL | RCC_PLLCFGR_PLL2FRACEN |

-             STM32_PLLCFGR_PLL1RGE | STM32_PLLCFGR_PLL1VCOSEL | RCC_PLLCFGR_PLL1FRACEN;

-

-#if STM32_PLL1_ENABLED == TRUE

     onmask  |= RCC_CR_PLL1ON;

     rdymask |= RCC_CR_PLL1RDY;

 #if STM32_PLL1_P_ENABLED == TRUE

@@ -273,9 +255,12 @@ void stm32_clock_init(void) {
 #if STM32_PLL1_R_ENABLED == TRUE

     cfgmask |= RCC_PLLCFGR_DIVR1EN;

 #endif

-#endif

+#endif /* STM32_PLL1_ENABLED == TRUE */

 

 #if STM32_PLL2_ENABLED == TRUE

+    RCC->PLL2FRACR = STM32_PLL2_FRACN;

+    RCC->PLL2DIVR  = STM32_PLL2_DIVR | STM32_PLL2_DIVQ |

+                     STM32_PLL2_DIVP | STM32_PLL2_DIVN;

     onmask  |= RCC_CR_PLL2ON;

     rdymask |= RCC_CR_PLL2RDY;

 #if STM32_PLL2_P_ENABLED == TRUE

@@ -287,9 +272,12 @@ void stm32_clock_init(void) {
 #if STM32_PLL2_R_ENABLED == TRUE

     cfgmask |= RCC_PLLCFGR_DIVR2EN;

 #endif

-#endif

+#endif /* STM32_PLL2_ENABLED == TRUE */

 

 #if STM32_PLL3_ENABLED == TRUE

+    RCC->PLL3FRACR = STM32_PLL3_FRACN;

+    RCC->PLL3DIVR  = STM32_PLL3_DIVR | STM32_PLL3_DIVQ |

+                     STM32_PLL3_DIVP | STM32_PLL3_DIVN;

     onmask  |= RCC_CR_PLL3ON;

     rdymask |= RCC_CR_PLL3RDY;

 #if STM32_PLL3_P_ENABLED == TRUE

@@ -301,7 +289,7 @@ void stm32_clock_init(void) {
 #if STM32_PLL3_R_ENABLED == TRUE

     cfgmask |= RCC_PLLCFGR_DIVR3EN;

 #endif

-#endif

+#endif /* STM32_PLL3_ENABLED == TRUE */

 

     /* Activating enabled PLLs and waiting for all of them to become ready.*/

     RCC->PLLCFGR = cfgmask & STM32_PLLCFGR_MASK;

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
index 639269b05..8b530d12e 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
@@ -363,6 +363,7 @@
 #define STM32_PLLSRC_HSI_CK             RCC_PLLCKSELR_PLLSRC_VALUE(0U)

 #define STM32_PLLSRC_CSI_CK             RCC_PLLCKSELR_PLLSRC_VALUE(1U)

 #define STM32_PLLSRC_HSE_CK             RCC_PLLCKSELR_PLLSRC_VALUE(2U)

+#define STM32_PLLSRC_DISABLE            RCC_PLLCKSELR_PLLSRC_VALUE(23U)

 

 #define STM32_CKPERSEL_HSI_CK           RCC_D1CCIPR_CKPERSEL_VALUE(0U)

 #define STM32_CKPERSEL_CSI_CK           RCC_D1CCIPR_CKPERSEL_VALUE(1U)