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authorGiovanni Di Sirio <gdisirio@gmail.com>2018-01-08 08:58:34 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2018-01-08 08:58:34 +0000
commit7761387ba0a0ac206b7e5ab133462c29882b63bd (patch)
tree158722e03054fb8b5727ff27dc5aae28eef13ce8 /os/hal/ports/STM32/STM32H7xx/stm32_registry.h
parent4148fb3cb7dcbe3eeef998bf6d0a86a1ad2447da (diff)
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Added unified cache handler for Cortex-M devices.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11233 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32H7xx/stm32_registry.h')
-rw-r--r--os/hal/ports/STM32/STM32H7xx/stm32_registry.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h
index 0a4af9460..8bee2a7d7 100644
--- a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h
@@ -87,8 +87,6 @@
#define STM32_BDMA1_CH7_NUMBER 136
/* DMA attributes.*/
-#define STM32_DMA_CACHE_HANDLING TRUE
-
#define STM32_HAS_DMA1 TRUE
#define STM32_DMA1_CH0_HANDLER Vector6C
#define STM32_DMA1_CH1_HANDLER Vector70