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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-11-10 09:52:11 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-11-10 09:52:11 +0000 |
| commit | d80425b576c14ec01a26cba643b4fcca62223e56 (patch) | |
| tree | e2d06a9371bca10cac888be18dc37575ab69fcc3 /os/hal/ports/STM32/STM32F7xx/hal_lld.h | |
| parent | 1ae8efe009e2c52a3a40e545a1516d09469af1e8 (diff) | |
| download | ChibiOS-d80425b576c14ec01a26cba643b4fcca62223e56.tar.gz ChibiOS-d80425b576c14ec01a26cba643b4fcca62223e56.tar.bz2 ChibiOS-d80425b576c14ec01a26cba643b4fcca62223e56.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8462 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F7xx/hal_lld.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F7xx/hal_lld.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h index dcd5beadd..f1c4bbfef 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h @@ -293,19 +293,19 @@ #define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */
#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */
#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/
-#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFF /**< LCD CLK is not required. */
+#define STM32_PLLSAIDIVR_OFF 0xFFFFFFFFU /**< LCD CLK is not required. */
#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */
#define STM32_SAI1SEL_SAIPLL (0 << 20) /**< SAI1 source is SAIPLL. */
#define STM32_SAI1SEL_I2SPLL (1 << 20) /**< SAI1 source is I2SPLL. */
#define STM32_SAI1SEL_CKIN (2 << 20) /**< SAI1 source is I2S_CKIN. */
-#define STM32_SAI1SEL_OFF 0xFFFFFFFF /**< SAI1 clock is not required.*/
+#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/
#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */
#define STM32_SAI2SEL_SAIPLL (0 << 22) /**< SAI2 source is SAIPLL. */
#define STM32_SAI2SEL_I2SPLL (1 << 22) /**< SAI2 source is I2SPLL. */
#define STM32_SAI2SEL_CKIN (2 << 22) /**< SAI2 source is I2S_CKIN. */
-#define STM32_SAI2SEL_OFF 0xFFFFFFFF /**< SAI2 clock is not required.*/
+#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/
#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */
#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */
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