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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-05-12 12:29:40 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-05-12 12:29:40 +0000 |
| commit | ca256de846f3bfa71c52b235db468ebb7e1f11fd (patch) | |
| tree | 17dfe3ecb6977b844e0da4f8de2e772fcce345d7 /os/hal/ports/STM32/STM32F4xx/stm32_registry.h | |
| parent | d6b969dac4bab057ba283ba93da5edb03b8c24a2 (diff) | |
| download | ChibiOS-ca256de846f3bfa71c52b235db468ebb7e1f11fd.tar.gz ChibiOS-ca256de846f3bfa71c52b235db468ebb7e1f11fd.tar.bz2 ChibiOS-ca256de846f3bfa71c52b235db468ebb7e1f11fd.zip | |
Reorganization of F4 port, not finished yet.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12026 110e8d01-0319-4d1e-a829-52ad28d1bb01
Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx/stm32_registry.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index affcb6d73..3d6638de3 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -92,6 +92,8 @@ /* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI TRUE
#define STM32_HAS_RCC_PLLI2S TRUE
+#define STM32_HAS_RCC_DCKCFGR TRU§E
+#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_I2SSRC TRUE
#define STM32_HAS_RCC_I2SPLLSRC FALSE
#define STM32_HAS_RCC_CK48MSEL TRUE
@@ -471,6 +473,8 @@ /* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI TRUE
#define STM32_HAS_RCC_PLLI2S TRUE
+#define STM32_HAS_RCC_DCKCFGR TRUE
+#define STM32_HAS_RCC_DCKCFGR2 TRUE
#define STM32_HAS_RCC_I2SSRC FALSE
#define STM32_HAS_RCC_I2SPLLSRC FALSE
#define STM32_HAS_RCC_CK48MSEL TRUE
@@ -825,6 +829,8 @@ /* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI TRUE
#define STM32_HAS_RCC_PLLI2S TRUE
+#define STM32_HAS_RCC_DCKCFGR TRUE
+#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_CK48MSEL_I2S FALSE
#define STM32_HAS_RCC_CK48MSEL_SAI FALSE
#define STM32_HAS_RCC_I2SSRC TRUE
@@ -1202,6 +1208,8 @@ /* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S TRUE
+#define STM32_HAS_RCC_DCKCFGR TRUE
+#define STM32_HAS_RCC_DCKCFGR2 TRUE
#define STM32_HAS_RCC_I2SSRC FALSE
#define STM32_HAS_RCC_I2SPLLSRC TRUE
#define STM32_HAS_RCC_CK48MSEL TRUE
@@ -1583,6 +1591,8 @@ /* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S TRUE
+#define STM32_HAS_RCC_DCKCFGR TRUE
+#define STM32_HAS_RCC_DCKCFGR2 TRUE
#define STM32_HAS_RCC_I2SSRC FALSE
#define STM32_HAS_RCC_I2SPLLSRC TRUE
#define STM32_HAS_RCC_CK48MSEL TRUE
@@ -1915,6 +1925,8 @@ /* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S TRUE
+#define STM32_HAS_RCC_DCKCFGR TRUE
+#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_I2SSRC TRUE
#define STM32_HAS_RCC_I2SPLLSRC FALSE
#define STM32_HAS_RCC_CK48MSEL FALSE
@@ -2221,6 +2233,8 @@ /* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S FALSE
+#define STM32_HAS_RCC_DCKCFGR TRUE
+#define STM32_HAS_RCC_DCKCFGR2 TRUE
#define STM32_HAS_RCC_CK48MSEL_I2S FALSE
#define STM32_HAS_RCC_CK48MSEL_SAI FALSE
#define STM32_HAS_RCC_I2SSRC FALSE
@@ -2499,6 +2513,8 @@ /* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S TRUE
+#define STM32_HAS_RCC_DCKCFGR FALSE
+#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_CK48MSEL_I2S FALSE
#define STM32_HAS_RCC_CK48MSEL_SAI FALSE
#define STM32_HAS_RCC_I2SSRC TRUE
@@ -2852,6 +2868,8 @@ /* Clock tree attributes.*/
#define STM32_HAS_RCC_PLLSAI FALSE
#define STM32_HAS_RCC_PLLI2S FALSE
+#define STM32_HAS_RCC_DCKCFGR FALSE
+#define STM32_HAS_RCC_DCKCFGR2 FALSE
#define STM32_HAS_RCC_I2SSRC FALSE
#define STM32_HAS_RCC_I2SPLLSRC FALSE
#define STM32_HAS_RCC_CK48MSEL FALSE
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