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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-06-26 08:15:18 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-06-26 08:15:18 +0000 |
| commit | 90527794f02f544505e34b89687401aeaa964e35 (patch) | |
| tree | c3f4ab4edff188e69475e8622c71f15046108060 /os/hal/ports/STM32/STM32F4xx/stm32_registry.h | |
| parent | c79855891422c7f11bb24a662667d5404c94fba6 (diff) | |
| download | ChibiOS-90527794f02f544505e34b89687401aeaa964e35.tar.gz ChibiOS-90527794f02f544505e34b89687401aeaa964e35.tar.bz2 ChibiOS-90527794f02f544505e34b89687401aeaa964e35.zip | |
Merged LTDC DMA2D code in STM32F4xx HAL.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8052 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx/stm32_registry.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index b875fe02a..c3fa55879 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -322,6 +322,12 @@ #define STM32_HAS_OTG1 TRUE
#define STM32_HAS_OTG2 TRUE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC TRUE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D TRUE
+
/* FSMC attributes.*/
#define STM32_HAS_FSMC TRUE
#define STM32_FSMC_IS_FMC TRUE
@@ -334,6 +340,7 @@ STM32_DMA_STREAM_ID_MSK(2, 6) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_FSMC_DMA_CHN 0x03010201
+
#endif /* defined(STM32F429_439xx) || defined(STM32F427_437xx) */
/*===========================================================================*/
@@ -591,6 +598,12 @@ #define STM32_HAS_OTG1 TRUE
#define STM32_HAS_OTG2 TRUE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
/* FSMC attributes.*/
#define STM32_HAS_FSMC TRUE
#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
@@ -602,6 +615,7 @@ STM32_DMA_STREAM_ID_MSK(2, 6) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_FSMC_DMA_CHN 0x03010201
+
#endif /* defined(STM32F40_41xxx) || defined(STM32F2XX) */
/*===========================================================================*/
@@ -815,8 +829,15 @@ #define STM32_HAS_OTG1 TRUE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
/* FSMC attributes.*/
#define STM32_HAS_FSMC FALSE
+
#endif /* defined(STM32F401xx) */
/*===========================================================================*/
@@ -1029,8 +1050,15 @@ #define STM32_HAS_OTG1 TRUE
#define STM32_HAS_OTG2 FALSE
+/* LTDC attributes.*/
+#define STM32_HAS_LTDC FALSE
+
+/* DMA2D attributes.*/
+#define STM32_HAS_DMA2D FALSE
+
/* FSMC attributes.*/
#define STM32_HAS_FSMC FALSE
+
#endif
/** @} */
|