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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2016-05-26 12:57:35 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2016-05-26 12:57:35 +0000 |
| commit | 6f7ae6af72328f41ed3156206a7af738719fe9c8 (patch) | |
| tree | 8eb2847307013565b463e7fe0a0e1ea54a9ecd54 /os/hal/ports/STM32/STM32F4xx/stm32_registry.h | |
| parent | d22d4c839e7438786d23921641bdabffac4dd247 (diff) | |
| download | ChibiOS-6f7ae6af72328f41ed3156206a7af738719fe9c8.tar.gz ChibiOS-6f7ae6af72328f41ed3156206a7af738719fe9c8.tar.bz2 ChibiOS-6f7ae6af72328f41ed3156206a7af738719fe9c8.zip | |
QUADSPI settings in all registries and platform.mk.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9535 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx/stm32_registry.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index eb9ce86a5..c48f815a7 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -217,6 +217,13 @@ #define STM32_HAS_I2C4 FALSE
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector1AC
+#define STM32_QUADSPI1_NUMBER 91
+#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_QUADSPI1_DMA_CHN 0x30000000
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@@ -571,6 +578,13 @@ #define STM32_HAS_I2C4 FALSE
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 TRUE
+#define STM32_QUADSPI1_HANDLER Vector1AC
+#define STM32_QUADSPI1_NUMBER 91
+#define STM32_QUADSPI1_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 7)
+#define STM32_QUADSPI1_DMA_CHN 0x30000000
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@@ -906,6 +920,9 @@ #define STM32_HAS_I2C4 FALSE
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@@ -1268,6 +1285,9 @@ #define STM32_HAS_I2C4 FALSE
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#if !defined(STM32F2XX)
@@ -1584,6 +1604,9 @@ #define STM32_HAS_I2C4 FALSE
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@@ -1865,6 +1888,9 @@ STM32_DMA_STREAM_ID_MSK(1, 1))
#define STM32_I2C4_TX_DMA_CHN 0x00040020
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
@@ -2123,6 +2149,9 @@ #define STM32_HAS_I2C4 FALSE
+/* QUADSPI attributes.*/
+#define STM32_HAS_QUADSPI1 FALSE
+
/* RTC attributes.*/
#define STM32_HAS_RTC TRUE
#define STM32_RTC_HAS_SUBSECONDS TRUE
|