Reorganization of F4 port, not finished yet.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@12026 110e8d01-0319-4d1e-a829-52ad28d1bb01

1 files changed, 96 insertions, 57 deletions

diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
index 9c8545dfc..5bf326b92 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -448,8 +448,9 @@
 #define STM32_PLLI2SP_DIV6      (2 << 16)   /**< PLLI2S clock divided by 6. */

 #define STM32_PLLI2SP_DIV8      (3 << 16)   /**< PLLI2S clock divided by 8. */

 #define STM32_PLLI2SSRC_MASK    (1 << 22)   /**< PLLI2SSRC mask.            */

-#define STM32_PLLI2SSRC_CKIN    (0 << 22)   /**< PLLI2SSRC is CK_IN.        */

-#define STM32_PLLI2SSRC_I2SCKIN (1 << 22)   /**< PLLI2SSRC is I2S_CKIN.     */

+#define STM32_PLLI2SSRC_PLLSRC  (0 << 22)   /**< PLLI2SSRC is selected PLL

+                                                 source.                    */

+#define STM32_PLLI2SSRC_CKIN    (1 << 22)   /**< PLLI2SSRC is I2S_CKIN.     */

 #define STM32_PLLI2SQ_MASK      (15 << 24)  /**< PLLI2SQ mask.              */

 #define STM32_PLLI2SR_MASK      (7 << 28)   /**< PLLI2SR mask.              */

 /** @} */

@@ -484,9 +485,13 @@
  * @name    RCC_DCKCFGR register bits definitions

  * @{

  */

+#if !defined(STM32F413xx) || defined(_DOXYGEN__)

 #define STM32_PLLI2SDIVQ_MASK   (31 << 0)   /**< PLLI2SDIVQ mask.           */

-

 #define STM32_PLLSAIDIVQ_MASK   (31 << 8)   /**< PLLSAIDIVQ mask.           */

+#else

+#define STM32_PLLI2SDIVR_MASK   (31 << 0)

+#define STM32_PLLSAIDIVR_MASK   (31 << 8)

+#endif

 

 #define STM32_PLLSAIDIVR_MASK   (3 << 16)   /**< PLLSAIDIVR mask.           */

 #define STM32_PLLSAIDIVR_DIV2   (0 << 16)   /**< LCD_CLK is R divided by 2. */

@@ -760,13 +765,32 @@
 #endif /* !defined(STM32F4XX) */

 

 /**

- * @brief   I2S clock source.

- */

+ * @brief   I2S clock source (post-PLL).

+ * @note    Not all devices have this setting, it is alternative to

+ *          @p STM32_PLLI2SSRC.

+  */

 #if !defined(STM32_I2SSRC) || defined(__DOXYGEN__)

 #define STM32_I2SSRC                STM32_I2SSRC_CKIN

 #endif

 

 /**

+ * @brief   I2S clock source (pre-PLL).

+ * @note    Not all devices have this setting, it is alternative to

+ *          @p STM32_I2SSRC.

+ */

+#if !defined(STM32_PLLI2SSRC) || defined(__DOXYGEN__)

+#define STM32_PLLI2SSRC             STM32_PLLI2SSRC_CKIN

+#endif

+

+/**

+ * @brief   I2S external clock value, zero if not present.

+ * @note    Not all devices have this setting.

+ */

+#if !defined(STM32_I2SCKIN_VALUE) || defined(__DOXYGEN__)

+#define STM32_I2SCKIN_VALUE         0

+#endif

+

+/**

  * @brief   PLLI2SN multiplier value.

  * @note    The allowed values are 192..432, except for

  *          STM32F446 where values are 50...432.

@@ -814,10 +838,11 @@
 #endif

 

 /**

- * @brief   STM32_PLLI2SDIVQ divider value (SAI clock divider).

+ * @brief   PLLI2SDIVQ divider value (SAI clock divider).

+ * @note    The allowed values are 1..32.

  */

-#if !defined(STM32_PLLI2SDIVQ) || defined(__DOXYGEN__)

-#define STM32_PLLI2SDIVQ            0

+#if !defined(STM32_PLLI2SDIVQ_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLI2SDIVQ_VALUE      1

 #endif

 

 /**

@@ -882,14 +907,16 @@
 #endif

 

 /**

- * @brief   PLLSAIDIVR divider value (LCD clock divider).

+ * @brief   PLLSAIDIVQ divider value (LCD clock divider).

+ * @note    The allowed values are 1..32.

  */

-#if !defined(STM32_PLLSAIDIVQ) || defined(__DOXYGEN__)

-#define STM32_PLLSAIDIVQ            0

+#if !defined(STM32_PLLSAIDIVQ_VALUE) || defined(__DOXYGEN__)

+#define STM32_PLLSAIDIVQ_VALUE      1

 #endif

 

 /**

  * @brief   SAI1SEL value (SAI1 clock source).

+ * @todo    Add check.

  */

 #if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__)

 #define STM32_SAI1SEL               STM32_SAI1SEL_OFF

@@ -897,6 +924,7 @@
 

 /**

  * @brief   SAI2SEL value (SAI2 clock source).

+ * @todo    Add check.

  */

 #if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__)

 #define STM32_SAI2SEL               STM32_SAI2SEL_OFF

@@ -1406,6 +1434,17 @@
 #endif /* !STM32_LSE_ENABLED */

 

 /**

+ * @brief   Clock frequency feeding PLLs.

+ */

+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

+#define STM32_PLLSRCCLK             STM32_HSECLK

+#elif STM32_PLLSRC == STM32_PLLSRC_HSI

+#define STM32_PLLSRCCLK             STM32_HSICLK

+#else

+#error "invalid STM32_PLLSRC value specified"

+#endif

+

+/**

  * @brief   STM32_PLLM field.

  */

 #if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) ||                \

@@ -1418,13 +1457,7 @@
 /**

  * @brief   PLL input clock frequency.

  */

-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

-#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PLLM_VALUE)

-#elif STM32_PLLSRC == STM32_PLLSRC_HSI

-#define STM32_PLLCLKIN              (STM32_HSICLK / STM32_PLLM_VALUE)

-#else

-#error "invalid STM32_PLLSRC value specified"

-#endif

+#define STM32_PLLCLKIN              (STM32_PLLSRCCLK / STM32_PLLM_VALUE)

 

 /*

  * PLLs input frequency range check.

@@ -1574,7 +1607,7 @@
 #endif

 #define STM32_OVERDRIVE_REQUIRED    FALSE

 

-#elif defined(STM32F410xx) || defined(STM32F411xx) ||                      \

+#elif defined(STM32F410xx) || defined(STM32F411xx) ||                       \

       defined(STM32F412xx) || defined(STM32F413xx)

 #if STM32_SYSCLK <= 64000000

 #define STM32_VOS                   STM32_VOS_SCALE3

@@ -1673,13 +1706,13 @@
  * PLLI2S enable check.

  */

 #if (STM32_HAS_RCC_PLLI2S &&                                                \

-     STM32_CLOCK48_REQUIRED &&                                              \

-     (STM32_HAS_RCC_CK48MSEL &&                                             \

-      STM32_RCC_CK48MSEL_USES_I2S &&                                        \

-      (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) ||                         \

-     (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) ||                               \

-     (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) ||                             \

-     (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S)) ||                            \

+     (STM32_CLOCK48_REQUIRED &&                                             \

+      (STM32_HAS_RCC_CK48MSEL &&                                            \

+       STM32_RCC_CK48MSEL_USES_I2S &&                                       \

+       (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) ||                        \

+      (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) ||                              \

+      (STM32_SAI1SEL == STM32_SAI1SEL_PLLI2S) ||                            \

+      (STM32_SAI2SEL == STM32_SAI2SEL_PLLI2S))) ||                          \

     defined(__DOXYGEN__)

 

 /**

@@ -1703,21 +1736,12 @@
 /**

  * @brief   STM32_PLLI2SN field.

  */

-#if defined(STM32F446xx) || defined(STM32F413xx) || defined(__DOXYGEN__)

-#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) ||       \

-    defined(__DOXYGEN__)

-#define STM32_PLLI2SN               (STM32_PLLI2SN_VALUE << 6)

-#else

-#error "invalid STM32_PLLI2SN_VALUE value specified"

-#endif

-#else  /* !(defined(STM32F446xx) || defined(STM32F413xx)) */

-#if ((STM32_PLLI2SN_VALUE >= 192) && (STM32_PLLI2SN_VALUE <= 432)) ||       \

+#if ((STM32_PLLI2SN_VALUE >= 50) && (STM32_PLLI2SN_VALUE <= 432)) ||        \

     defined(__DOXYGEN__)

 #define STM32_PLLI2SN               (STM32_PLLI2SN_VALUE << 6)

 #else

 #error "invalid STM32_PLLI2SN_VALUE value specified"

 #endif

-#endif  /* !(defined(STM32F446xx) || defined(STM32F413xx)) */

 

 /**

  * @brief   STM32_PLLI2SP field.

@@ -1745,6 +1769,16 @@
 #endif

 

 /**

+ * @brief   STM32_PLLI2SDIVQ field.

+ */

+#if ((STM32_PLLI2SDIVQ_VALUE >= 1) && (STM32_PLLI2SDIVQ_VALUE <= 32)) ||    \

+    defined(__DOXYGEN__)

+#define STM32_PLLI2SDIVQ            ((STM32_PLLI2SQ_VALUE - 1) << 0)

+#else

+#error "invalid STM32_PLLI2SDIVQ_VALUE value specified"

+#endif

+

+/**

  * @brief   STM32_PLLI2SR field.

  */

 #if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) ||           \

@@ -1757,23 +1791,17 @@
 /**

  * @brief   PLLI2S input clock frequency.

  */

-#if defined(STM32F446xx) || defined(STM32F413xx)

-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

-#define STM32_PLLI2SCLKIN           (STM32_HSECLK / STM32_PLLI2SM_VALUE)

-#elif STM32_PLLSRC == STM32_PLLSRC_HSI

-#define STM32_PLLI2SCLKIN           (STM32_HSICLK / STM32_PLLI2SM_VALUE)

+#if STM32_HAS_RCC_I2SPLLSRC || defined(__DOXYGEN__)

+#if (STM32_PLLI2SSRC == STM32_PLLI2SSRC_PLLSRC) || defined(__DOXYGEN__)

+#define STM32_PLLI2SCLKIN           (STM32_PLLSRCCLK / STM32_PLLI2SM_VALUE)

+#elif STM32_PLLI2SSRC == STM32_PLLI2SSRC_I2SCKIN

+#define STM32_PLLI2SCLKIN           (STM32_I2SCKIN_VALUE / STM32_PLLI2SM_VALUE)

 #else

-#error "invalid STM32_PLLSRC value specified"

+#error "invalid STM32_PLLI2SSRC value specified"

 #endif

-#else /* !(defined(STM32F446xx) || defined(STM32F413xx)) */

-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)

-#define STM32_PLLI2SCLKIN           (STM32_HSECLK / STM32_PLLM_VALUE)

-#elif STM32_PLLSRC == STM32_PLLSRC_HSI

-#define STM32_PLLI2SCLKIN           (STM32_HSICLK / STM32_PLLM_VALUE)

 #else

-#error "invalid STM32_PLLSRC value specified"

+#define STM32_PLLI2SCLKIN           (STM32_PLLSRCCLK / STM32_PLLM_VALUE)

 #endif

-#endif /* !(defined(STM32F446xx) || defined(STM32F413xx)) */

 

 /**

  * @brief   PLLI2S VCO frequency.

@@ -1807,13 +1835,14 @@
  * PLLSAI enable check.

  */

 #if (STM32_HAS_RCC_PLLSAI &&                                                \

-     STM32_CLOCK48_REQUIRED &&                                              \

-     (STM32_HAS_RCC_CK48MSEL &&                                             \

-      !STM32_RCC_CK48MSEL_USES_I2S &&                                       \

-      (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) ||                         \

-     (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) ||                               \

-     (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) ||                             \

-     (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI)) ||                            \

+     (STM32_CLOCK48_REQUIRED &&                                             \

+      (STM32_HAS_RCC_CK48MSEL &&                                            \

+       !STM32_RCC_CK48MSEL_USES_I2S &&                                      \

+       (STM32_CK48MSEL == STM32_CK48MSEL_PLLALT)) ||                        \

+      (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) ||                              \

+      (STM32_SAI1SEL == STM32_SAI1SEL_PLLSAI) ||                            \

+      (STM32_SAI2SEL == STM32_SAI2SEL_PLLSAI))) ||                          \

+      (STM32_PLLSAIDIVR != STM32_PLLSAIDIVR_OFF) ||                         \

     defined(__DOXYGEN__)

 /**

  * @brief   PLLSAI activation flag.

@@ -1826,7 +1855,7 @@
 /**

  * @brief   STM32_PLLSAIM field.

  */

-#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) ||        \

+#if ((STM32_PLLSAIM_VALUE >= 2) && (STM32_PLLSAIM_VALUE <= 63)) ||          \

     defined(__DOXYGEN__)

 #define STM32_PLLSAIM               (STM32_PLLSAIM_VALUE << 0)

 #else

@@ -1854,6 +1883,16 @@
 #endif

 

 /**

+ * @brief   STM32_PLLSAIDIVQ_VALUE field.

+ */

+#if ((STM32_PLLSAIDIVQ_VALUE >= 1) && (STM32_PLLSAIDIVQ_VALUE <= 32)) ||    \

+    defined(__DOXYGEN__)

+#define STM32_PLLSAIDIVQ            ((STM32_PLLSAIDIVQ_VALUE - 1) << 8)

+#else

+#error "invalid STM32_PLLSAIDIVQ_VALUE value specified"

+#endif

+

+/**

  * @brief   STM32_PLLSAIR field.

  */

 #if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) ||           \