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| author | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2016-05-23 16:34:18 +0000 |
|---|---|---|
| committer | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2016-05-23 16:34:18 +0000 |
| commit | b36f9f55856979ae773c8c676c0f6723440e52a1 (patch) | |
| tree | c098cf7e3248cd62207b8fa40bd54b56ab25fa12 /os/hal/ports/STM32/STM32F4xx/hal_lld.h | |
| parent | 055f0a587ad0f2a84ef53b500dff7b5e637a41aa (diff) | |
| download | ChibiOS-b36f9f55856979ae773c8c676c0f6723440e52a1.tar.gz ChibiOS-b36f9f55856979ae773c8c676c0f6723440e52a1.tar.bz2 ChibiOS-b36f9f55856979ae773c8c676c0f6723440e52a1.zip | |
Fixed Bug #742
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9507 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx/hal_lld.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/hal_lld.h | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index ade9e8b40..5883c99e4 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -425,17 +425,11 @@ #define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */
#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */
-#define STM32_MCO2SEL_MASK (3U << 30) /**< MCO2 mask. */
-#define STM32_MCO2SEL_SYSCLK (0U << 30) /**< SYSCLK clock on MCO2 pin. */
-#define STM32_MCO2SEL_PLLI2S (1U << 30) /**< PLLI2S clock on MCO2 pin. */
-#define STM32_MCO2SEL_HSE (2U << 30) /**< HSE clock on MCO2 pin. */
-#define STM32_MCO2SEL_PLL (3U << 30) /**< PLL clock on MCO2 pin. */
-
-#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */
-#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */
-#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */
-#define STM32_RTC_HSE (3 << 8) /**< HSE divided by programmable
- prescaler used as RTC clock*/
+#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */
+#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */
+#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */
+#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */
+#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */
/**
* @name RCC_PLLI2SCFGR register bits definitions
|