diff options
| author | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2016-05-24 19:35:29 +0000 |
|---|---|---|
| committer | Rocco Marco Guglielmi <roccomarco.guglielmi@live.com> | 2016-05-24 19:35:29 +0000 |
| commit | 8c8a1441fd198586aa1abd0e4b1231ac3445355b (patch) | |
| tree | 53641d6d62b79d53f8ab01e21dc1af45ef68295d /os/hal/ports/STM32/STM32F4xx/hal_lld.h | |
| parent | e0f986d17ab0251eb30bfb83cccdc72243a81164 (diff) | |
| download | ChibiOS-8c8a1441fd198586aa1abd0e4b1231ac3445355b.tar.gz ChibiOS-8c8a1441fd198586aa1abd0e4b1231ac3445355b.tar.bz2 ChibiOS-8c8a1441fd198586aa1abd0e4b1231ac3445355b.zip | |
Fixed Bug #744
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9518 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx/hal_lld.h')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/hal_lld.h | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h index 0104a78d2..9387336bb 100644 --- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h @@ -404,13 +404,6 @@ #define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */
#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */
-#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
-#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
-#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
-#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
-#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
-#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
-
#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */
#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */
#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */
@@ -440,6 +433,19 @@ /** @} */
/**
+ * @name RCC_PLLSAICFGR register bits definitions
+ * @{
+ */
+#define STM32_SAIR_DIV2 (0 << 16) /**< R divided by 2. */
+#define STM32_SAIR_DIV4 (1 << 16) /**< R divided by 4. */
+#define STM32_SAIR_DIV8 (2 << 16) /**< R divided by 8. */
+#define STM32_SAIR_DIV16 (3 << 16) /**< R divided by 16. */
+
+#define STM32_SAISRC_NOCLOCK (0 << 23) /**< No clock. */
+#define STM32_SAISRC_PLL (1 << 23) /**< SAI_CKIN is PLL. */
+/** @} */
+
+/**
* @name RCC_BDCR register bits definitions
* @{
*/
|