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authorGiovanni Di Sirio <gdisirio@gmail.com>2015-06-26 08:15:18 +0000
committerGiovanni Di Sirio <gdisirio@gmail.com>2015-06-26 08:15:18 +0000
commit90527794f02f544505e34b89687401aeaa964e35 (patch)
treec3f4ab4edff188e69475e8622c71f15046108060 /os/hal/ports/STM32/STM32F4xx/hal_lld.c
parentc79855891422c7f11bb24a662667d5404c94fba6 (diff)
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Merged LTDC DMA2D code in STM32F4xx HAL.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8052 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx/hal_lld.c')
-rw-r--r--os/hal/ports/STM32/STM32F4xx/hal_lld.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index 4bb3f4fcd..03cd5f06f 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -232,6 +232,17 @@ void stm32_clock_init(void) {
;
#endif
+#if STM32_ACTIVATE_PLLSAI
+ /* PLLSAI activation.*/
+ RCC->PLLSAICFGR = STM32_PLLSAIN | STM32_PLLSAIR | STM32_PLLSAIQ;
+ RCC->DCKCFGR = (RCC->DCKCFGR & ~RCC_DCKCFGR_PLLSAIDIVR) | STM32_PLLSAIR_POST;
+ RCC->CR |= RCC_CR_PLLSAION;
+
+ /* Waiting for PLL lock.*/
+ while (!(RCC->CR & RCC_CR_PLLSAIRDY))
+ ;
+#endif
+
/* Other clock-related settings (dividers, MCO etc).*/
RCC->CFGR = STM32_MCO2PRE | STM32_MCO2SEL | STM32_MCO1PRE | STM32_MCO1SEL |
STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | STM32_HPRE;