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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-02-10 14:57:35 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-02-10 14:57:35 +0000 |
| commit | 607e3a4c20df279c6c317f9bb0f554c6dde6a6c5 (patch) | |
| tree | 1d1d8ad8966d4ce55f8a65994bad68de122d4347 /os/hal/ports/STM32/STM32F4xx/adc_lld.c | |
| parent | 6eb46acf16600aedba6608bc06f6eab0892a43e9 (diff) | |
| download | ChibiOS-607e3a4c20df279c6c317f9bb0f554c6dde6a6c5.tar.gz ChibiOS-607e3a4c20df279c6c317f9bb0f554c6dde6a6c5.tar.bz2 ChibiOS-607e3a4c20df279c6c317f9bb0f554c6dde6a6c5.zip | |
Safer ADC start for STM32F4 and STM32L1.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7677 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F4xx/adc_lld.c')
| -rw-r--r-- | os/hal/ports/STM32/STM32F4xx/adc_lld.c | 23 |
1 files changed, 16 insertions, 7 deletions
diff --git a/os/hal/ports/STM32/STM32F4xx/adc_lld.c b/os/hal/ports/STM32/STM32F4xx/adc_lld.c index 29992bbdb..65556b1a3 100644 --- a/os/hal/ports/STM32/STM32F4xx/adc_lld.c +++ b/os/hal/ports/STM32/STM32F4xx/adc_lld.c @@ -317,6 +317,7 @@ void adc_lld_stop(ADCDriver *adcp) { */
void adc_lld_start_conversion(ADCDriver *adcp) {
uint32_t mode;
+ uint32_t cr2;
const ADCConversionGroup *grpp = adcp->grpp;
/* DMA setup.*/
@@ -343,15 +344,23 @@ void adc_lld_start_conversion(ADCDriver *adcp) { adcp->adc->SQR2 = grpp->sqr2;
adcp->adc->SQR3 = grpp->sqr3;
- /* ADC configuration and start, the start is performed using the method
- specified in the CR2 configuration, usually ADC_CR2_SWSTART.*/
+ /* ADC configuration and start.*/
adcp->adc->CR1 = grpp->cr1 | ADC_CR1_OVRIE | ADC_CR1_SCAN;
- if ((grpp->cr2 & ADC_CR2_SWSTART) != 0)
- adcp->adc->CR2 = grpp->cr2 | ADC_CR2_CONT | ADC_CR2_DMA |
- ADC_CR2_DDS | ADC_CR2_ADON;
+
+ /* Enforcing the mandatory bits in CR2.*/
+ cr2 = grpp->cr2 | ADC_CR2_DMA | ADC_CR2_DDS | ADC_CR2_ADON;
+
+ /* The start method is different dependign if HW or SW triggered, the
+ start is performed using the method specified in the CR2 configuration.*/
+ if ((cr2 & ADC_CR2_SWSTART) != 0) {
+ /* Initializing CR2 while keeping ADC_CR2_SWSTART at zero.*/
+ adcp->adc->CR2 = (cr2 | ADC_CR2_CONT) & ~ADC_CR2_SWSTART;
+
+ /* Finally enabling ADC_CR2_SWSTART.*/
+ adcp->adc->CR2 = (cr2 | ADC_CR2_CONT);
+ }
else
- adcp->adc->CR2 = grpp->cr2 | ADC_CR2_DMA |
- ADC_CR2_DDS | ADC_CR2_ADON;
+ adcp->adc->CR2 = cr2;
}
/**
|