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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-17 14:55:12 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2018-01-17 14:55:12 +0000 |
| commit | c953aa5ac86e4f913c41333a773a0903e0860d35 (patch) | |
| tree | d2c00d4f0eaf25892e5d4f4ade85b2866e2c38de /os/hal/ports/STM32/STM32F3xx | |
| parent | df330879bb5c5630e847e2e9eec471080b0d18a4 (diff) | |
| download | ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.tar.gz ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.tar.bz2 ChibiOS-c953aa5ac86e4f913c41333a773a0903e0860d35.zip | |
Defaulted all STM32 drivers to enable peripheral clocks during stop/sleep modes. Now RCC macros are able to set or clear the LP bit of a peripheral.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11300 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F3xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32F3xx/hal_lld.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.c b/os/hal/ports/STM32/STM32F3xx/hal_lld.c index 33424ae05..a409285e6 100644 --- a/os/hal/ports/STM32/STM32F3xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.c @@ -112,7 +112,7 @@ void hal_lld_init(void) { rccResetAPB2(0xFFFFFFFF);
/* PWR clock enabled.*/
- rccEnablePWRInterface(FALSE);
+ rccEnablePWRInterface(true);
/* Initializes the backup domain.*/
hal_lld_backup_domain_init();
@@ -132,7 +132,7 @@ void hal_lld_init(void) { /* SYSCFG clock enabled here because it is a multi-functional unit shared
among multiple drivers.*/
- rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+ rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, true);
#if STM32_HAS_USB
/* USB IRQ relocated to not conflict with CAN.*/
|