diff options
| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-01-11 10:32:33 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2017-01-11 10:32:33 +0000 |
| commit | b4e1ecc760fb1dea0089428a4ba4cdd9510e1cdb (patch) | |
| tree | 4961f4098fc1c1cd8ef9bf499ef27ed0b2a6e4fe /os/hal/ports/STM32/STM32F37x | |
| parent | ed83337999ec1cd8ee7c66a5d6b11b9a2abf9f36 (diff) | |
| download | ChibiOS-b4e1ecc760fb1dea0089428a4ba4cdd9510e1cdb.tar.gz ChibiOS-b4e1ecc760fb1dea0089428a4ba4cdd9510e1cdb.tar.bz2 ChibiOS-b4e1ecc760fb1dea0089428a4ba4cdd9510e1cdb.zip | |
Various STM32 timers-related fixes into registry and RCC files.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10030 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F37x')
| -rw-r--r-- | os/hal/ports/STM32/STM32F37x/stm32_rcc.h | 154 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F37x/stm32_registry.h | 16 |
2 files changed, 159 insertions, 11 deletions
diff --git a/os/hal/ports/STM32/STM32F37x/stm32_rcc.h b/os/hal/ports/STM32/STM32F37x/stm32_rcc.h index 716b64e89..5310ab103 100644 --- a/os/hal/ports/STM32/STM32F37x/stm32_rcc.h +++ b/os/hal/ports/STM32/STM32F37x/stm32_rcc.h @@ -709,7 +709,6 @@ * @api
*/
#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
-/** @} */
/**
* @brief Enables the TIM7 peripheral clock.
@@ -735,7 +734,6 @@ * @api
*/
#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
-/** @} */
/**
* @brief Enables the TIM12 peripheral clock.
@@ -761,7 +759,32 @@ * @api
*/
#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST)
-/** @} */
+
+/**
+ * @brief Enables the TIM13 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Disables the TIM13 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp)
+
+/**
+ * @brief Resets the TIM13 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST)
+
/**
* @brief Enables the TIM14 peripheral clock.
@@ -787,6 +810,131 @@ * @api
*/
#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST)
+
+/**
+ * @brief Enables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM15(lp) rccEnableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Disables the TIM15 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM15(lp) rccDisableAPB2(RCC_APB2ENR_TIM15EN, lp)
+
+/**
+ * @brief Resets the TIM15 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM15() rccResetAPB2(RCC_APB2RSTR_TIM15RST)
+
+/**
+ * @brief Enables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM16(lp) rccEnableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Disables the TIM16 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM16(lp) rccDisableAPB2(RCC_APB2ENR_TIM16EN, lp)
+
+/**
+ * @brief Resets the TIM16 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM16() rccResetAPB2(RCC_APB2RSTR_TIM16RST)
+
+/**
+ * @brief Enables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM17(lp) rccEnableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Disables the TIM17 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM17(lp) rccDisableAPB2(RCC_APB2ENR_TIM17EN, lp)
+
+/**
+ * @brief Resets the TIM17 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM17() rccResetAPB2(RCC_APB2RSTR_TIM17RST)
+
+/**
+ * @brief Enables the TIM18 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM18(lp) rccEnableAPB1(RCC_APB1ENR_TIM18EN, lp)
+
+/**
+ * @brief Disables the TIM18 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM18(lp) rccDisableAPB1(RCC_APB1ENR_TIM18EN, lp)
+
+/**
+ * @brief Resets the TIM18 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM18() rccResetAPB1(RCC_APB1RSTR_TIM18RST)
+
+/**
+ * @brief Enables the TIM19 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM19(lp) rccEnableAPB2(RCC_APB2ENR_TIM19EN, lp)
+
+/**
+ * @brief Disables the TIM19 peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM19(lp) rccDisableAPB2(RCC_APB2ENR_TIM19EN, lp)
+
+/**
+ * @brief Resets the TIM19 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM19() rccResetAPB2(RCC_APB2RSTR_TIM19RST)
/** @} */
/**
diff --git a/os/hal/ports/STM32/STM32F37x/stm32_registry.h b/os/hal/ports/STM32/STM32F37x/stm32_registry.h index 3f22e5c79..55ba86766 100644 --- a/os/hal/ports/STM32/STM32F37x/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F37x/stm32_registry.h @@ -204,11 +204,11 @@ #define STM32_HAS_TIM13 TRUE
#define STM32_TIM13_IS_32BITS FALSE
-#define STM32_TIM13_CHANNELS 2
+#define STM32_TIM13_CHANNELS 1
#define STM32_HAS_TIM14 TRUE
#define STM32_TIM14_IS_32BITS FALSE
-#define STM32_TIM14_CHANNELS 2
+#define STM32_TIM14_CHANNELS 1
#define STM32_HAS_TIM15 TRUE
#define STM32_TIM15_IS_32BITS FALSE
@@ -216,11 +216,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM18 TRUE
#define STM32_TIM18_IS_32BITS FALSE
@@ -456,11 +456,11 @@ #define STM32_HAS_TIM13 TRUE
#define STM32_TIM13_IS_32BITS FALSE
-#define STM32_TIM13_CHANNELS 2
+#define STM32_TIM13_CHANNELS 1
#define STM32_HAS_TIM14 TRUE
#define STM32_TIM14_IS_32BITS FALSE
-#define STM32_TIM14_CHANNELS 2
+#define STM32_TIM14_CHANNELS 1
#define STM32_HAS_TIM15 TRUE
#define STM32_TIM15_IS_32BITS FALSE
@@ -468,11 +468,11 @@ #define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
-#define STM32_TIM16_CHANNELS 2
+#define STM32_TIM16_CHANNELS 1
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
-#define STM32_TIM17_CHANNELS 2
+#define STM32_TIM17_CHANNELS 1
#define STM32_HAS_TIM18 TRUE
#define STM32_TIM18_IS_32BITS FALSE
|