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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-07-28 14:22:57 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2015-07-28 14:22:57 +0000 |
| commit | 5b7d62c5490a3f4662c1ba77ab3f78a80ad6869d (patch) | |
| tree | dffae619b098255689af0ae2dddfdad4166c4d70 /os/hal/ports/STM32/STM32F0xx | |
| parent | 402bd03481bb1d0b062e72eab2d24d714b846285 (diff) | |
| download | ChibiOS-5b7d62c5490a3f4662c1ba77ab3f78a80ad6869d.tar.gz ChibiOS-5b7d62c5490a3f4662c1ba77ab3f78a80ad6869d.tar.bz2 ChibiOS-5b7d62c5490a3f4662c1ba77ab3f78a80ad6869d.zip | |
Updated EXT driver.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8121 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/ports/STM32/STM32F0xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c | 60 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h | 13 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32F0xx/stm32_registry.h | 2 |
3 files changed, 67 insertions, 8 deletions
diff --git a/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c index be5d76a09..99fd15cf5 100644 --- a/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c +++ b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c @@ -130,6 +130,7 @@ OSAL_IRQ_HANDLER(Vector5C) { OSAL_IRQ_EPILOGUE();
}
+#if !defined(STM32F030) || defined(__DOXYGEN__)
/**
* @brief EXTI[16] interrupt handler (PVD).
*
@@ -144,21 +145,70 @@ OSAL_IRQ_HANDLER(Vector44) { OSAL_IRQ_EPILOGUE();
}
+#endif
+#if !defined(STM32_DISABLE_EXTI171920_HANDLER)
/**
- * @brief EXTI[17] interrupt handler (RTC).
+ * @brief EXTI[17],EXTI[19],EXTI[20] interrupt handler (RTC).
*
* @isr
*/
OSAL_IRQ_HANDLER(Vector48) {
+ uint32_t pr;
OSAL_IRQ_PROLOGUE();
- EXTI->PR = (1 << 17);
- EXTD1.config->channels[17].cb(&EXTD1, 17);
+ pr = EXTI->PR & EXTI->IMR & ((1 << 17) | (1 << 19) | (1 << 20));
+ EXTI->PR = pr;
+ if (pr & (1 << 17))
+ EXTD1.config->channels[17].cb(&EXTD1, 17);
+ if (pr & (1 << 19))
+ EXTD1.config->channels[19].cb(&EXTD1, 19);
+ if (pr & (1 << 20))
+ EXTD1.config->channels[20].cb(&EXTD1, 20);
OSAL_IRQ_EPILOGUE();
}
+#endif
+#endif /* HAL_USE_EXT */
+
+#if (HAL_USE_EXT || HAL_USE_ADC) || defined(__DOXYGEN__)
+#if !defined(STM32F030) || defined(__DOXYGEN__)
+#if !defined(STM32_DISABLE_EXTI2122_HANDLER)
+/**
+ * @brief EXTI[21],EXTI[22] interrupt handler (ADC, COMP).
+ * @note This handler is shared with the ADC so it is handled
+ * a bit differently.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector70) {
+
+ OSAL_IRQ_PROLOGUE();
+
+#if HAL_USE_EXT
+ {
+ uint32_t pr;
+
+ pr = EXTI->PR & EXTI->IMR & ((1 << 21) | (1 << 22));
+ EXTI->PR = pr;
+ if (pr & (1 << 21))
+ EXTD1.config->channels[21].cb(&EXTD1, 21);
+ if (pr & (1 << 22))
+ EXTD1.config->channels[21].cb(&EXTD1, 22);
+ }
+#endif
+#if HAL_USE_ADC
+ adc_lld_serve_interrupt(&ADCD1);
+#endif
+
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+#endif /* !defined(STM32F030) */
+#endif /* HAL_USE_EXT || HAL_USE_ADC */
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
/*===========================================================================*/
/* Driver exported functions. */
@@ -176,8 +226,9 @@ void ext_lld_exti_irq_enable(void) { nvicEnableVector(EXTI4_15_IRQn, STM32_EXT_EXTI4_15_IRQ_PRIORITY);
#if !defined(STM32F030)
nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+ nvicEnableVector(ADC1_COMP_IRQn, STM32_EXT_EXTI21_22_IRQ_PRIORITY);
#endif
- nvicEnableVector(RTC_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+ nvicEnableVector(RTC_IRQn, STM32_EXT_EXTI17_20_IRQ_PRIORITY);
}
/**
@@ -192,6 +243,7 @@ void ext_lld_exti_irq_disable(void) { nvicDisableVector(EXTI4_15_IRQn);
#if !defined(STM32F030)
nvicDisableVector(PVD_IRQn);
+ nvicDisableVector(ADC1_COMP_IRQn);
#endif
nvicDisableVector(RTC_IRQn);
}
diff --git a/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h index b9282e15d..4adc03597 100644 --- a/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h +++ b/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.h @@ -68,10 +68,17 @@ #endif
/**
- * @brief EXTI17 interrupt priority level setting.
+ * @brief EXTI17,19,20 interrupt priority level setting.
*/
-#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI17_IRQ_PRIORITY 3
+#if !defined(STM32_EXT_EXTI17_20_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_20_IRQ_PRIORITY 3
+#endif
+
+/**
+ * @brief EXTI21,22 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI21_22_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI21_22_IRQ_PRIORITY 3
#endif
/** @} */
diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h index 7874cef34..a7abd8e25 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h @@ -902,7 +902,7 @@ /* EXTI attributes.*/
#define STM32_EXTI_NUM_LINES 20
-#define STM32_EXTI_IMR_MASK 0xFFF40000U
+#define STM32_EXTI_IMR_MASK 0xFFF50000U
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
|