git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8123 35acf78f-673a-0410-8e92-d51de3d6d3f4

6 files changed, 75 insertions, 1370 deletions

diff --git a/os/hal/ports/STM32/STM32F0xx/adc_lld.c b/os/hal/ports/STM32/STM32F0xx/adc_lld.c
deleted file mode 100644
index c4d5de47e..000000000
--- a/os/hal/ports/STM32/STM32F0xx/adc_lld.c
+++ /dev/null
@@ -1,297 +0,0 @@
-/*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-

-    Licensed under the Apache License, Version 2.0 (the "License");

-    you may not use this file except in compliance with the License.

-    You may obtain a copy of the License at

-

-        http://www.apache.org/licenses/LICENSE-2.0

-

-    Unless required by applicable law or agreed to in writing, software

-    distributed under the License is distributed on an "AS IS" BASIS,

-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-    See the License for the specific language governing permissions and

-    limitations under the License.

-*/

-

-/**

- * @file    STM32F0xx/adc_lld.c

- * @brief   STM32F0xx ADC subsystem low level driver source.

- *

- * @addtogroup ADC

- * @{

- */

-

-#include "hal.h"

-

-#if HAL_USE_ADC || defined(__DOXYGEN__)

-

-/*===========================================================================*/

-/* Driver local definitions.                                                 */

-/*===========================================================================*/

-

-/*===========================================================================*/

-/* Driver exported variables.                                                */

-/*===========================================================================*/

-

-/** @brief ADC1 driver identifier.*/

-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)

-ADCDriver ADCD1;

-#endif

-

-/*===========================================================================*/

-/* Driver local variables and types.                                         */

-/*===========================================================================*/

-

-/*===========================================================================*/

-/* Driver local functions.                                                   */

-/*===========================================================================*/

-

-/**

- * @brief   Stops an ongoing conversion, if any.

- *

- * @param[in] adc       pointer to the ADC registers block

- */

-static void adc_lld_stop_adc(ADC_TypeDef *adc) {

-

-  if (adc->CR & ADC_CR_ADSTART) {

-    adc->CR |= ADC_CR_ADSTP;

-    while (adc->CR & ADC_CR_ADSTP)

-      ;

-  }

-}

-

-/**

- * @brief   ADC DMA ISR service routine.

- *

- * @param[in] adcp      pointer to the @p ADCDriver object

- * @param[in] flags     pre-shifted content of the ISR register

- */

-static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {

-

-  /* DMA errors handling.*/

-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {

-    /* DMA, this could help only if the DMA tries to access an unmapped

-       address space or violates alignment rules.*/

-    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);

-  }

-  else {

-    /* It is possible that the conversion group has already be reset by the

-       ADC error handler, in this case this interrupt is spurious.*/

-    if (adcp->grpp != NULL) {

-      if ((flags & STM32_DMA_ISR_TCIF) != 0) {

-        /* Transfer complete processing.*/

-        _adc_isr_full_code(adcp);

-      }

-      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {

-        /* Half transfer processing.*/

-        _adc_isr_half_code(adcp);

-      }

-    }

-  }

-}

-

-/*===========================================================================*/

-/* Driver interrupt handlers.                                                */

-/*===========================================================================*/

-

-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)

-/**

- * @brief   ADC interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector70) {

-  uint32_t isr;

-

-  OSAL_IRQ_PROLOGUE();

-

-  isr = ADC1->ISR;

-  ADC1->ISR = isr;

-

-  /* It could be a spurious interrupt caused by overflows after DMA disabling,

-     just ignore it in this case.*/

-  if (ADCD1.grpp != NULL) {

-    /* Note, an overflow may occur after the conversion ended before the driver

-       is able to stop the ADC, this is why the DMA channel is checked too.*/

-    if ((isr & ADC_ISR_OVR) &&

-        (dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {

-      /* ADC overflow condition, this could happen only if the DMA is unable

-         to read data fast enough.*/

-      _adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);

-    }

-    if (isr & ADC_ISR_AWD) {

-      /* Analog watchdog error.*/

-      _adc_isr_error_code(&ADCD1, ADC_ERR_AWD);

-    }

-  }

-

-  OSAL_IRQ_EPILOGUE();

-}

-#endif

-

-/*===========================================================================*/

-/* Driver exported functions.                                                */

-/*===========================================================================*/

-

-/**

- * @brief   Low level ADC driver initialization.

- *

- * @notapi

- */

-void adc_lld_init(void) {

-

-#if STM32_ADC_USE_ADC1

-  /* Driver initialization.*/

-  adcObjectInit(&ADCD1);

-  ADCD1.adc = ADC1;

-  ADCD1.dmastp  = STM32_DMA1_STREAM1;

-  ADCD1.dmamode = STM32_DMA_CR_PL(STM32_ADC_ADC1_DMA_PRIORITY) |

-                  STM32_DMA_CR_DIR_P2M |

-                  STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD |

-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |

-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;

-#endif

-

-  /* The shared vector is initialized on driver initialization and never

-     disabled.*/

-  nvicEnableVector(12, STM32_ADC_IRQ_PRIORITY);

-

-  /* Calibration procedure.*/

-  rccEnableADC1(FALSE);

-  osalDbgAssert(ADC1->CR == 0, "invalid register state");

-  ADC1->CR |= ADC_CR_ADCAL;

-  while (ADC1->CR & ADC_CR_ADCAL)

-    ;

-  rccDisableADC1(FALSE);

-}

-

-/**

- * @brief   Configures and activates the ADC peripheral.

- *

- * @param[in] adcp      pointer to the @p ADCDriver object

- *

- * @notapi

- */

-void adc_lld_start(ADCDriver *adcp) {

-

-  /* If in stopped state then enables the ADC and DMA clocks.*/

-  if (adcp->state == ADC_STOP) {

-#if STM32_ADC_USE_ADC1

-    if (&ADCD1 == adcp) {

-      bool b;

-      b = dmaStreamAllocate(adcp->dmastp,

-                            STM32_ADC_ADC1_DMA_IRQ_PRIORITY,

-                            (stm32_dmaisr_t)adc_lld_serve_rx_interrupt,

-                            (void *)adcp);

-      osalDbgAssert(!b, "stream already allocated");

-      dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);

-      rccEnableADC1(FALSE);

-#if STM32_ADCSW == STM32_ADCSW_HSI14

-      /* Clock from HSI14, no need for jitter removal.*/

-      ADC1->CFGR2 = 0;

-#else

-#if STM32_ADCPRE == STM32_ADCPRE_DIV2

-      ADC1->CFGR2 = ADC_CFGR2_JITOFFDIV2;

-#else

-      ADC1->CFGR2 = ADC_CFGR2_JITOFFDIV4;

-#endif

-#endif

-    }

-#endif /* STM32_ADC_USE_ADC1 */

-

-    /* ADC initial setup, starting the analog part here in order to reduce

-       the latency when starting a conversion.*/

-    adcp->adc->CR = ADC_CR_ADEN;

-    while (!(adcp->adc->ISR & ADC_ISR_ADRDY))

-      ;

-  }

-}

-

-/**

- * @brief   Deactivates the ADC peripheral.

- *

- * @param[in] adcp      pointer to the @p ADCDriver object

- *

- * @notapi

- */

-void adc_lld_stop(ADCDriver *adcp) {

-

-  /* If in ready state then disables the ADC clock and analog part.*/

-  if (adcp->state == ADC_READY) {

-

-    dmaStreamRelease(adcp->dmastp);

-

-    /* Disabling ADC.*/

-    if (adcp->adc->CR & ADC_CR_ADEN) {

-      adc_lld_stop_adc(adcp->adc);

-      adcp->adc->CR |= ADC_CR_ADDIS;

-      while (adcp->adc->CR & ADC_CR_ADDIS)

-        ;

-    }

-

-#if STM32_ADC_USE_ADC1

-    if (&ADCD1 == adcp)

-      rccDisableADC1(FALSE);

-#endif

-  }

-}

-

-/**

- * @brief   Starts an ADC conversion.

- *

- * @param[in] adcp      pointer to the @p ADCDriver object

- *

- * @notapi

- */

-void adc_lld_start_conversion(ADCDriver *adcp) {

-  uint32_t mode, cfgr1;

-  const ADCConversionGroup *grpp = adcp->grpp;

-

-  /* DMA setup.*/

-  mode  = adcp->dmamode;

-  cfgr1 = grpp->cfgr1 | ADC_CFGR1_DMAEN;

-  if (grpp->circular) {

-    mode  |= STM32_DMA_CR_CIRC;

-    cfgr1 |= ADC_CFGR1_DMACFG;

-    if (adcp->depth > 1) {

-      /* If circular buffer depth > 1, then the half transfer interrupt

-         is enabled in order to allow streaming processing.*/

-      mode |= STM32_DMA_CR_HTIE;

-    }

-  }

-  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);

-  dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *

-                                            (uint32_t)adcp->depth);

-  dmaStreamSetMode(adcp->dmastp, mode);

-  dmaStreamEnable(adcp->dmastp);

-

-  /* ADC setup, if it is defined a callback for the analog watch dog then it

-     is enabled.*/

-  adcp->adc->ISR    = adcp->adc->ISR;

-  adcp->adc->IER    = ADC_IER_OVRIE | ADC_IER_AWDIE;

-  adcp->adc->TR     = grpp->tr;

-  adcp->adc->SMPR   = grpp->smpr;

-  adcp->adc->CHSELR = grpp->chselr;

-

-  /* ADC configuration and start.*/

-  adcp->adc->CFGR1  = cfgr1;

-  adcp->adc->CR    |= ADC_CR_ADSTART;

-}

-

-/**

- * @brief   Stops an ongoing conversion.

- *

- * @param[in] adcp      pointer to the @p ADCDriver object

- *

- * @notapi

- */

-void adc_lld_stop_conversion(ADCDriver *adcp) {

-

-  dmaStreamDisable(adcp->dmastp);

-  adc_lld_stop_adc(adcp->adc);

-}

-

-#endif /* HAL_USE_ADC */

-

-/** @} */

diff --git a/os/hal/ports/STM32/STM32F0xx/adc_lld.h b/os/hal/ports/STM32/STM32F0xx/adc_lld.h
deleted file mode 100644
index 8b9141a76..000000000
--- a/os/hal/ports/STM32/STM32F0xx/adc_lld.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-

-    Licensed under the Apache License, Version 2.0 (the "License");

-    you may not use this file except in compliance with the License.

-    You may obtain a copy of the License at

-

-        http://www.apache.org/licenses/LICENSE-2.0

-

-    Unless required by applicable law or agreed to in writing, software

-    distributed under the License is distributed on an "AS IS" BASIS,

-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-    See the License for the specific language governing permissions and

-    limitations under the License.

-*/

-

-/**

- * @file    STM32F0xx/adc_lld.h

- * @brief   STM32F0xx ADC subsystem low level driver header.

- *

- * @addtogroup ADC

- * @{

- */

-

-#ifndef _ADC_LLD_H_

-#define _ADC_LLD_H_

-

-#if HAL_USE_ADC || defined(__DOXYGEN__)

-

-/*===========================================================================*/

-/* Driver constants.                                                         */

-/*===========================================================================*/

-

-/**

- * @name    Sampling rates

- * @{

- */

-#define ADC_SMPR_SMP_1P5        0   /**< @brief 14 cycles conversion time   */

-#define ADC_SMPR_SMP_7P5        1   /**< @brief 21 cycles conversion time.  */

-#define ADC_SMPR_SMP_13P5       2   /**< @brief 28 cycles conversion time.  */

-#define ADC_SMPR_SMP_28P5       3   /**< @brief 41 cycles conversion time.  */

-#define ADC_SMPR_SMP_41P5       4   /**< @brief 54 cycles conversion time.  */

-#define ADC_SMPR_SMP_55P5       5   /**< @brief 68 cycles conversion time.  */

-#define ADC_SMPR_SMP_71P5       6   /**< @brief 84 cycles conversion time.  */

-#define ADC_SMPR_SMP_239P5      7   /**< @brief 252 cycles conversion time. */

-/** @} */

-

-/**

- * @name    CFGR1 register configuration helpers

- * @{

- */

-#define ADC_CFGR1_RES_12BIT             (0 << 3)

-#define ADC_CFGR1_RES_10BIT             (1 << 3)

-#define ADC_CFGR1_RES_8BIT              (2 << 3)

-#define ADC_CFGR1_RES_6BIT              (3 << 3)

-

-#define ADC_CFGR1_EXTSEL_MASK           (15 << 6)

-#define ADC_CFGR1_EXTSEL_SRC(n)         ((n) << 6)

-

-#define ADC_CFGR1_EXTEN_MASK            (3 << 10)

-#define ADC_CFGR1_EXTEN_DISABLED        (0 << 10)

-#define ADC_CFGR1_EXTEN_RISING          (1 << 10)

-#define ADC_CFGR1_EXTEN_FALLING         (2 << 10)

-#define ADC_CFGR1_EXTEN_BOTH            (3 << 10)

-/** @} */

-

-/**

- * @name    Threashold register initializer

- * @{

- */

-#define ADC_TR(low, high)               (((uint32_t)(high) << 16) |         \

-                                         (uint32_t)(low))

-/** @} */

-

-/*===========================================================================*/

-/* Driver pre-compile time settings.                                         */

-/*===========================================================================*/

-

-/**

- * @name    Configuration options

- * @{

- */

-/**

- * @brief   ADC1 driver enable switch.

- * @details If set to @p TRUE the support for ADC1 is included.

- * @note    The default is @p FALSE.

- */

-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)

-#define STM32_ADC_USE_ADC1                  FALSE

-#endif

-

-/**

- * @brief   ADC1 DMA priority (0..3|lowest..highest).

- */

-#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC1_DMA_PRIORITY         2

-#endif

-

-/**

- * @brief   ADC interrupt priority level setting.

- */

-#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_IRQ_PRIORITY              2

-#endif

-

-/**

- * @brief   ADC1 DMA interrupt priority level setting.

- */

-#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)

-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     2

-#endif

-

-/** @} */

-

-/*===========================================================================*/

-/* Derived constants and error checks.                                       */

-/*===========================================================================*/

-

-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1

-#error "ADC1 not present in the selected device"

-#endif

-

-#if !STM32_ADC_USE_ADC1

-#error "ADC driver activated but no ADC peripheral assigned"

-#endif

-

-#if STM32_ADC_USE_ADC1 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to ADC1"

-#endif

-

-#if STM32_ADC_USE_ADC1 &&                                                   \

-    !OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)

-#error "Invalid IRQ priority assigned to ADC1 DMA"

-#endif

-

-#if STM32_ADC_USE_ADC1 &&                                                   \

-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)

-#error "Invalid DMA priority assigned to ADC1"

-#endif

-

-#if !defined(STM32_DMA_REQUIRED)

-#define STM32_DMA_REQUIRED

-#endif

-

-/*===========================================================================*/

-/* Driver data structures and types.                                         */

-/*===========================================================================*/

-

-/**

- * @brief   ADC sample data type.

- */

-typedef uint16_t adcsample_t;

-

-/**

- * @brief   Channels number in a conversion group.

- */

-typedef uint16_t adc_channels_num_t;

-

-/**

- * @brief   Possible ADC failure causes.

- * @note    Error codes are architecture dependent and should not relied

- *          upon.

- */

-typedef enum {

-  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */

-  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */

-  ADC_ERR_AWD = 2                           /**< Analog watchdog triggered. */

-} adcerror_t;

-

-/**

- * @brief   Type of a structure representing an ADC driver.

- */

-typedef struct ADCDriver ADCDriver;

-

-/**

- * @brief   ADC notification callback type.

- *

- * @param[in] adcp      pointer to the @p ADCDriver object triggering the

- *                      callback

- * @param[in] buffer    pointer to the most recent samples data

- * @param[in] n         number of buffer rows available starting from @p buffer

- */

-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);

-

-/**

- * @brief   ADC error callback type.

- *

- * @param[in] adcp      pointer to the @p ADCDriver object triggering the

- *                      callback

- * @param[in] err       ADC error code

- */

-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);

-

-/**

- * @brief   Conversion group configuration structure.

- * @details This implementation-dependent structure describes a conversion

- *          operation.

- * @note    The use of this configuration structure requires knowledge of

- *          STM32 ADC cell registers interface, please refer to the STM32

- *          reference manual for details.

- */

-typedef struct {

-  /**

-   * @brief   Enables the circular buffer mode for the group.

-   */

-  bool                      circular;

-  /**

-   * @brief   Number of the analog channels belonging to the conversion group.

-   */

-  adc_channels_num_t        num_channels;

-  /**

-   * @brief   Callback function associated to the group or @p NULL.

-   */

-  adccallback_t             end_cb;

-  /**

-   * @brief   Error callback or @p NULL.

-   */

-  adcerrorcallback_t        error_cb;

-  /* End of the mandatory fields.*/

-  /**

-   * @brief   ADC CFGR1 register initialization data.

-   * @note    The bits DMAEN and DMACFG are enforced internally

-   *          to the driver, keep them to zero.

-   * @note    The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be

-   *          specified in continuous more or if the buffer depth is

-   *          greater than one.

-   */

-  uint32_t                  cfgr1;

-  /**

-   * @brief   ADC TR register initialization data.

-   */

-  uint32_t                  tr;

-  /**

-   * @brief   ADC SMPR register initialization data.

-   */

-  uint32_t                  smpr;

-  /**

-   * @brief   ADC CHSELR register initialization data.

-   * @details The number of bits at logic level one in this register must

-   *          be equal to the number in the @p num_channels field.

-   */

-  uint32_t                  chselr;

-} ADCConversionGroup;

-

-/**

- * @brief   Driver configuration structure.

- * @note    It could be empty on some architectures.

- */

-typedef struct {

-  uint32_t                  dummy;

-} ADCConfig;

-

-/**

- * @brief   Structure representing an ADC driver.

- */

-struct ADCDriver {

-  /**

-   * @brief Driver state.

-   */

-  adcstate_t                state;

-  /**

-   * @brief Current configuration data.

-   */

-  const ADCConfig           *config;

-  /**

-   * @brief Current samples buffer pointer or @p NULL.

-   */

-  adcsample_t               *samples;

-  /**

-   * @brief Current samples buffer depth or @p 0.

-   */

-  size_t                    depth;

-  /**

-   * @brief Current conversion group pointer or @p NULL.

-   */

-  const ADCConversionGroup  *grpp;

-#if ADC_USE_WAIT || defined(__DOXYGEN__)

-  /**

-   * @brief Waiting thread.

-   */

-  thread_reference_t        thread;

-#endif

-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)

-  /**

-   * @brief Mutex protecting the peripheral.

-   */

-  mutex_t                   mutex;

-#endif /* ADC_USE_MUTUAL_EXCLUSION */

-#if defined(ADC_DRIVER_EXT_FIELDS)

-  ADC_DRIVER_EXT_FIELDS

-#endif

-  /* End of the mandatory fields.*/

-  /**

-   * @brief Pointer to the ADCx registers block.

-   */

-  ADC_TypeDef               *adc;

-  /**

-   * @brief Pointer to associated DMA channel.

-   */

-  const stm32_dma_stream_t  *dmastp;

-  /**

-   * @brief DMA mode bit mask.

-   */

-  uint32_t                  dmamode;

-};

-

-/*===========================================================================*/

-/* Driver macros.                                                            */

-/*===========================================================================*/

-

-/**

- * @brief   Changes the value of the ADC CCR register.

- * @details Use this function in order to enable or disable the internal

- *          analog sources. See the documentation in the STM32F0xx Reference

- *          Manual.

- */

-#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr))

-

-/*===========================================================================*/

-/* External declarations.                                                    */

-/*===========================================================================*/

-

-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)

-extern ADCDriver ADCD1;

-#endif

-

-#ifdef __cplusplus

-extern "C" {

-#endif

-  void adc_lld_init(void);

-  void adc_lld_start(ADCDriver *adcp);

-  void adc_lld_stop(ADCDriver *adcp);

-  void adc_lld_start_conversion(ADCDriver *adcp);

-  void adc_lld_stop_conversion(ADCDriver *adcp);

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* HAL_USE_ADC */

-

-#endif /* _ADC_LLD_H_ */

-

-/** @} */

diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk
index f7a35d22d..88eb3766e 100644
--- a/os/hal/ports/STM32/STM32F0xx/platform.mk
+++ b/os/hal/ports/STM32/STM32F0xx/platform.mk
@@ -3,9 +3,9 @@ ifeq ($(USE_SMART_BUILD),yes)
 HALCONF := $(strip $(shell cat halconf.h | egrep -e "define"))

 

 PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \

-               $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/stm32_dma.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c \

+               $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/TIMv1/st_lld.c

 ifneq ($(findstring HAL_USE_ADC TRUE,$(HALCONF)),)

 PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c

@@ -51,12 +51,12 @@ PLATFORMSRC += $(CHIBIOS)/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
 endif

 else

 PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \

-               $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/stm32_dma.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/hal_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/STM32F0xx/ext_lld_isr.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1/adc_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1/can_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1/dac_lld.c \

+               $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1/stm32_dma.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1/ext_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \

@@ -77,6 +77,7 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
                $(CHIBIOS)/os/hal/ports/STM32/LLD/ADCv1 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/CANv1 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/DACv1 \

+               $(CHIBIOS)/os/hal/ports/STM32/LLD/DMAv1 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/EXTIv1 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2 \

                $(CHIBIOS)/os/hal/ports/STM32/LLD/I2Cv2 \

diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_dma.c b/os/hal/ports/STM32/STM32F0xx/stm32_dma.c
deleted file mode 100644
index a6e562fed..000000000
--- a/os/hal/ports/STM32/STM32F0xx/stm32_dma.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-

-    Licensed under the Apache License, Version 2.0 (the "License");

-    you may not use this file except in compliance with the License.

-    You may obtain a copy of the License at

-

-        http://www.apache.org/licenses/LICENSE-2.0

-

-    Unless required by applicable law or agreed to in writing, software

-    distributed under the License is distributed on an "AS IS" BASIS,

-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-    See the License for the specific language governing permissions and

-    limitations under the License.

-*/

-

-/**

- * @file    STM32F0xx/stm32_dma.c

- * @brief   DMA helper driver code.

- *

- * @addtogroup STM32F0xx_DMA

- * @details DMA sharing helper driver. In the STM32 the DMA streams are a

- *          shared resource, this driver allows to allocate and free DMA

- *          streams at runtime in order to allow all the other device

- *          drivers to coordinate the access to the resource.

- * @note    The DMA ISR handlers are all declared into this module because

- *          sharing, the various device drivers can associate a callback to

- *          ISRs when allocating streams.

- * @{

- */

-

-#include "hal.h"

-

-/* The following macro is only defined if some driver requiring DMA services

-   has been enabled.*/

-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)

-

-/*===========================================================================*/

-/* Driver local definitions.                                                 */

-/*===========================================================================*/

-

-/**

- * @brief   Mask of the DMA1 streams in @p dma_streams_mask.

- */

-#define STM32_DMA1_STREAMS_MASK     0x0000007F

-

-/**

- * @brief   Mask of the DMA2 streams in @p dma_streams_mask.

- */

-#define STM32_DMA2_STREAMS_MASK     0x00000F80

-

-/**

- * @brief   Post-reset value of the stream CCR register.

- */

-#define STM32_DMA_CCR_RESET_VALUE   0x00000000

-

-/*===========================================================================*/

-/* Driver exported variables.                                                */

-/*===========================================================================*/

-

-/**

- * @brief   DMA streams descriptors.

- * @details This table keeps the association between an unique stream

- *          identifier and the involved physical registers.

- * @note    Don't use this array directly, use the appropriate wrapper macros

- *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.

- */

-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {

-  {DMA1_Channel1, &DMA1->IFCR, 0x0001, 0, 0, DMA1_Channel1_IRQn},

-  {DMA1_Channel2, &DMA1->IFCR, 0x0006, 4, 1, DMA1_Channel2_3_IRQn},

-  {DMA1_Channel3, &DMA1->IFCR, 0x0006, 8, 2, DMA1_Channel2_3_IRQn},

-  {DMA1_Channel4, &DMA1->IFCR, 0x0078, 12, 3, DMA1_Channel4_5_IRQn},

-  {DMA1_Channel5, &DMA1->IFCR, 0x0078, 16, 4, DMA1_Channel4_5_IRQn},

-#if STM32_DMA_STREAMS > 5

-  {DMA1_Channel6, &DMA1->IFCR, 0x0078, 20, 5, DMA1_Channel4_5_6_7_IRQn},

-  {DMA1_Channel7, &DMA1->IFCR, 0x0078, 24, 6, DMA1_Channel4_5_6_7_IRQn}

-#endif

-};

-

-/*===========================================================================*/

-/* Driver local variables and types.                                         */

-/*===========================================================================*/

-

-/**

- * @brief   DMA ISR redirector type.

- */

-typedef struct {

-  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */

-  void                  *dma_param;     /**< @brief DMA callback parameter. */

-} dma_isr_redir_t;

-

-/**

- * @brief   Mask of the allocated streams.

- */

-static uint32_t dma_streams_mask;

-

-/**

- * @brief   DMA IRQ redirectors.

- */

-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];

-

-/*===========================================================================*/

-/* Driver local functions.                                                   */

-/*===========================================================================*/

-

-/*===========================================================================*/

-/* Driver interrupt handlers.                                                */

-/*===========================================================================*/

-

-/**

- * @brief   DMA1 stream 1 shared interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector64) {

-  uint32_t flags;

-

-  OSAL_IRQ_PROLOGUE();

-

-  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;

-  DMA1->IFCR = flags << 0;

-  if (dma_isr_redir[0].dma_func)

-    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);

-

-  OSAL_IRQ_EPILOGUE();

-}

-

-/**

- * @brief   DMA1 streams 2 and 3 shared interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector68) {

-  uint32_t flags;

-

-  OSAL_IRQ_PROLOGUE();

-

-  /* Check on channel 2.*/

-  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;

-  if (flags & STM32_DMA_ISR_MASK) {

-    DMA1->IFCR = flags << 4;

-    if (dma_isr_redir[1].dma_func)

-      dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);

-  }

-

-  /* Check on channel 3.*/

-  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;

-  if (flags & STM32_DMA_ISR_MASK) {

-    DMA1->IFCR = flags << 8;

-    if (dma_isr_redir[2].dma_func)

-      dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);

-  }

-

-  OSAL_IRQ_EPILOGUE();

-}

-

-/**

- * @brief   DMA1 streams 4 and 5 shared interrupt handler.

- *

- * @isr

- */

-OSAL_IRQ_HANDLER(Vector6C) {

-  uint32_t flags;

-

-  OSAL_IRQ_PROLOGUE();

-

-  /* Check on channel 4.*/

-  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;

-  if (flags & STM32_DMA_ISR_MASK) {

-    DMA1->IFCR = flags << 12;

-    if (dma_isr_redir[3].dma_func)

-      dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);

-  }

-

-  /* Check on channel 5.*/

-  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;

-  if (flags & STM32_DMA_ISR_MASK) {

-    DMA1->IFCR = flags << 16;

-    if (dma_isr_redir[4].dma_func)

-      dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);

-  }

-

-#if STM32_DMA_STREAMS > 5

-  /* Check on channel 6.*/

-  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;

-  if (flags & STM32_DMA_ISR_MASK) {

-    DMA1->IFCR = flags << 20;

-    if (dma_isr_redir[5].dma_func)

-      dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);

-  }

-

-  /* Check on channel 7.*/

-  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;

-  if (flags & STM32_DMA_ISR_MASK) {

-    DMA1->IFCR = flags << 24;

-    if (dma_isr_redir[6].dma_func)

-      dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);

-  }

-#endif

-

-  OSAL_IRQ_EPILOGUE();

-}

-

-/*===========================================================================*/

-/* Driver exported functions.                                                */

-/*===========================================================================*/

-

-/**

- * @brief   STM32 DMA helper initialization.

- *

- * @init

- */

-void dmaInit(void) {

-  int i;

-

-  dma_streams_mask = 0U;

-  for (i = 0; i < STM32_DMA_STREAMS; i++) {

-    _stm32_dma_streams[i].channel->CCR = 0U;

-    dma_isr_redir[i].dma_func = NULL;

-  }

-  DMA1->IFCR = 0xFFFFFFFFU;

-}

-

-/**

- * @brief   Allocates a DMA stream.

- * @details The stream is allocated and, if required, the DMA clock enabled.

- *          The function also enables the IRQ vector associated to the stream

- *          and initializes its priority.

- * @pre     The stream must not be already in use or an error is returned.

- * @post    The stream is allocated and the default ISR handler redirected

- *          to the specified function.

- * @post    The stream ISR vector is enabled and its priority configured.

- * @post    The stream must be freed using @p dmaStreamRelease() before it can

- *          be reused with another peripheral.

- * @post    The stream is in its post-reset state.

- * @note    This function can be invoked in both ISR or thread context.

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] priority  IRQ priority mask for the DMA stream

- * @param[in] func      handling function pointer, can be @p NULL

- * @param[in] param     a parameter to be passed to the handling function

- * @return              The operation status.

- * @retval false        no error, stream taken.

- * @retval true         error, stream already taken.

- *

- * @special

- */

-bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,

-                       uint32_t priority,

-                       stm32_dmaisr_t func,

-                       void *param) {

-

-  osalDbgCheck(dmastp != NULL);

-

-  /* Checks if the stream is already taken.*/

-  if ((dma_streams_mask & (1U << (uint32_t)dmastp->selfindex)) != 0U) {

-    return true;

-  }

-

-  /* Marks the stream as allocated.*/

-  dma_isr_redir[dmastp->selfindex].dma_func  = func;

-  dma_isr_redir[dmastp->selfindex].dma_param = param;

-  dma_streams_mask |= (1U << (uint32_t)dmastp->selfindex);

-

-  /* Enabling DMA clocks required by the current streams set.*/

-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0U) {

-    rccEnableDMA1(false);

-  }

-

-  /* Putting the stream in a safe state.*/

-  dmaStreamDisable(dmastp);

-  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;

-

-  /* Enables the associated IRQ vector.*/

-  nvicEnableVector(dmastp->vector, priority);

-

-  return false;

-}

-

-/**

- * @brief   Releases a DMA stream.

- * @details The stream is freed and, if required, the DMA clock disabled.

- *          Trying to release a unallocated stream is an illegal operation

- *          and is trapped if assertions are enabled.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    The stream is again available.

- * @note    This function can be invoked in both ISR or thread context.

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- *

- * @special

- */

-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {

-

-  osalDbgCheck(dmastp != NULL);

-

-  /* Check if the streams is not taken.*/

-  osalDbgAssert((dma_streams_mask & (1U << (uint32_t)dmastp->selfindex)) != 0U,

-                "not allocated");

-

-  /* Marks the stream as not allocated.*/

-  dma_streams_mask &= ~(1U << (uint32_t)dmastp->selfindex);

-

-  /* Disables the associated IRQ vector if also the sharing channels are

-     also disabled.*/

-  if ((dma_streams_mask & dmastp->sharedmask) == 0U) {

-    nvicDisableVector(dmastp->vector);

-  }

-

-  /* Shutting down clocks that are no more required, if any.*/

-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0U) {

-    rccDisableDMA1(false);

-  }

-}

-

-#endif /* STM32_DMA_REQUIRED */

-

-/** @} */

diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_dma.h b/os/hal/ports/STM32/STM32F0xx/stm32_dma.h
deleted file mode 100644
index 85463277f..000000000
--- a/os/hal/ports/STM32/STM32F0xx/stm32_dma.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*

-    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio

-

-    Licensed under the Apache License, Version 2.0 (the "License");

-    you may not use this file except in compliance with the License.

-    You may obtain a copy of the License at

-

-        http://www.apache.org/licenses/LICENSE-2.0

-

-    Unless required by applicable law or agreed to in writing, software

-    distributed under the License is distributed on an "AS IS" BASIS,

-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

-    See the License for the specific language governing permissions and

-    limitations under the License.

-*/

-

-/**

- * @file    STM32F0xx/stm32_dma.h

- * @brief   DMA helper driver header.

- * @note    This file requires definitions from the ST header file stm32f0xx.h.

- * @note    This driver uses the new naming convention used for the STM32F2xx

- *          so the "DMA channels" are referred as "DMA streams".

- *

- * @addtogroup STM32F0xx_DMA

- * @{

- */

-

-#ifndef _STM32_DMA_H_

-#define _STM32_DMA_H_

-

-/*===========================================================================*/

-/* Driver constants.                                                         */

-/*===========================================================================*/

-

-/**

- * @brief   Mask of the ISR bits passed to the DMA callback functions.

- */

-#define STM32_DMA_ISR_MASK          0x0F

-

-/**

- * @brief   Returns the channel associated to the specified stream.

- *

- * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)

- * @param[in] c         a stream/channel association word, one channel per

- *                      nibble, not associated channels must be set to 0xF

- * @return              Always zero, in this platform there is no dynamic

- *                      association between streams and channels.

- */

-#define STM32_DMA_GETCHANNEL(n, c)  0

-

-/**

- * @brief   Checks if a DMA priority is within the valid range.

- * @param[in] prio      DMA priority

- *

- * @retval              The check result.

- * @retval FALSE        invalid DMA priority.

- * @retval TRUE         correct DMA priority.

- */

-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))

-

-/**

- * @brief   Returns an unique numeric identifier for a DMA stream.

- *

- * @param[in] dma       the DMA unit number

- * @param[in] stream    the stream number

- * @return              An unique numeric stream identifier.

- */

-#define STM32_DMA_STREAM_ID(dma, stream) ((stream) - 1)

-

-/**

- * @brief   Returns a DMA stream identifier mask.

- *

- *

- * @param[in] dma       the DMA unit number

- * @param[in] stream    the stream number

- * @return              A DMA stream identifier mask.

- */

-#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \

-  (1 << STM32_DMA_STREAM_ID(dma, stream))

-

-/**

- * @brief   Checks if a DMA stream unique identifier belongs to a mask.

- * @param[in] id        the stream numeric identifier

- * @param[in] mask      the stream numeric identifiers mask

- *

- * @retval              The check result.

- * @retval FALSE        id does not belong to the mask.

- * @retval TRUE         id belongs to the mask.

- */

-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))

-

-/**

- * @name    DMA streams identifiers

- * @{

- */

-/**

- * @brief   Returns a pointer to a stm32_dma_stream_t structure.

- *

- * @param[in] id        the stream numeric identifier

- * @return              A pointer to the stm32_dma_stream_t constant structure

- *                      associated to the DMA stream.

- */

-#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])

-

-#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)

-#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)

-#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)

-#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)

-#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)

-#if (STM32_DMA_STREAMS > 5) || defined(__DOXYGEN__)

-#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)

-#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)

-#endif

-/** @} */

-

-/**

- * @name    CR register constants common to all DMA types

- * @{

- */

-#define STM32_DMA_CR_EN             DMA_CCR_EN

-#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE

-#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE

-#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE

-#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)

-#define STM32_DMA_CR_DIR_P2M        0

-#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR

-#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM

-#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC

-#define STM32_DMA_CR_PINC           DMA_CCR_PINC

-#define STM32_DMA_CR_MINC           DMA_CCR_MINC

-#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE

-#define STM32_DMA_CR_PSIZE_BYTE     0

-#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0

-#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1

-#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE

-#define STM32_DMA_CR_MSIZE_BYTE     0

-#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0

-#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1

-#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \

-                                     STM32_DMA_CR_MSIZE_MASK)

-#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL

-#define STM32_DMA_CR_PL(n)          ((n) << 12)

-/** @} */

-

-/**

- * @name    CR register constants only found in enhanced DMA

- * @{

- */

-#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */

-#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */

-#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */

-/** @} */

-

-/**

- * @name    Status flags passed to the ISR callbacks

- * @{

- */

-#define STM32_DMA_ISR_FEIF          0

-#define STM32_DMA_ISR_DMEIF         0

-#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1

-#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1

-#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1

-/** @} */

-

-/*===========================================================================*/

-/* Driver pre-compile time settings.                                         */

-/*===========================================================================*/

-

-/*===========================================================================*/

-/* Derived constants and error checks.                                       */

-/*===========================================================================*/

-

-#if !defined(STM32_ADVANCED_DMA)

-#error "missing STM32_ADVANCED_DMA definition in registry"

-#endif

-

-#if !defined(STM32_DMA_STREAMS)

-#error "missing STM32_DMA_STREAMS definition in registry"

-#endif

-

-#if STM32_ADVANCED_DMA == TRUE

-#error "DMAv1 driver does not support STM32_ADVANCED_DMA"

-#endif

-

-/*===========================================================================*/

-/* Driver data structures and types.                                         */

-/*===========================================================================*/

-

-/**

- * @brief   STM32 DMA stream descriptor structure.

- */

-typedef struct {

-  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */

-  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */

-  uint32_t              sharedmask;     /**< @brief Mask of channels sharing

-                                             the same ISR.                  */

-  uint8_t               ishift;         /**< @brief Bits offset in xIFCR

-                                             register.                      */

-  uint8_t               selfindex;      /**< @brief Index to self in array. */

-  uint8_t               vector;         /**< @brief Associated IRQ vector.  */

-} stm32_dma_stream_t;

-

-/**

- * @brief   STM32 DMA ISR function type.

- *

- * @param[in] p         parameter for the registered function

- * @param[in] flags     pre-shifted content of the ISR register, the bits

- *                      are aligned to bit zero

- */

-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);

-

-/*===========================================================================*/

-/* Driver macros.                                                            */

-/*===========================================================================*/

-

-/**

- * @name    Macro Functions

- * @{

- */

-/**

- * @brief   Associates a peripheral data register to a DMA stream.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] addr      value to be written in the CPAR register

- *

- * @special

- */

-#define dmaStreamSetPeripheral(dmastp, addr) {                              \

-  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \

-}

-

-/**

- * @brief   Associates a memory destination to a DMA stream.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] addr      value to be written in the CMAR register

- *

- * @special

- */

-#define dmaStreamSetMemory0(dmastp, addr) {                                 \

-  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \

-}

-

-/**

- * @brief   Sets the number of transfers to be performed.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] size      value to be written in the CNDTR register

- *

- * @special

- */

-#define dmaStreamSetTransactionSize(dmastp, size) {                         \

-  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \

-}

-

-/**

- * @brief   Returns the number of transfers to be performed.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @return              The number of transfers to be performed.

- *

- * @special

- */

-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))

-

-/**

- * @brief   Programs the stream mode settings.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] mode      value to be written in the CCR register

- *

- * @special

- */

-#define dmaStreamSetMode(dmastp, mode) {                                    \

-  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \

-}

-

-/**

- * @brief   DMA stream enable.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- *

- * @special

- */

-#define dmaStreamEnable(dmastp) {                                           \

-  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \

-}

-

-/**

- * @brief   DMA stream disable.

- * @details The function disables the specified stream and then clears any

- *          pending interrupt.

- * @note    This function can be invoked in both ISR or thread context.

- * @note    Interrupts enabling flags are set to zero after this call, see

- *          bug 3607518.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- *

- * @special

- */

-#define dmaStreamDisable(dmastp) {                                          \

-  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \

-                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \

-  dmaStreamClearInterrupt(dmastp);                                          \

-}

-

-/**

- * @brief   DMA stream interrupt sources clear.

- * @note    This function can be invoked in both ISR or thread context.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- *

- * @special

- */

-#define dmaStreamClearInterrupt(dmastp) {                                   \

-  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \

-}

-

-/**

- * @brief   Starts a memory to memory operation using the specified stream.

- * @note    The default transfer data mode is "byte to byte" but it can be

- *          changed by specifying extra options in the @p mode parameter.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- * @param[in] mode      value to be written in the CCR register, this value

- *                      is implicitly ORed with:

- *                      - @p STM32_DMA_CR_MINC

- *                      - @p STM32_DMA_CR_PINC

- *                      - @p STM32_DMA_CR_DIR_M2M

- *                      - @p STM32_DMA_CR_EN

- *                      .

- * @param[in] src       source address

- * @param[in] dst       destination address

- * @param[in] n         number of data units to copy

- */

-#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \

-  dmaStreamSetPeripheral(dmastp, src);                                      \

-  dmaStreamSetMemory0(dmastp, dst);                                         \

-  dmaStreamSetTransactionSize(dmastp, n);                                   \

-  dmaStreamSetMode(dmastp, (mode) |                                         \

-                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \

-                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \

-}

-

-/**

- * @brief   Polled wait for DMA transfer end.

- * @pre     The stream must have been allocated using @p dmaStreamAllocate().

- * @post    After use the stream can be released using @p dmaStreamRelease().

- *

- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure

- */

-#define dmaWaitCompletion(dmastp) {                                         \

-  while ((dmastp)->channel->CNDTR > 0)                                      \

-    ;                                                                       \

-  dmaStreamDisable(dmastp);                                                 \

-}

-/** @} */

-

-/*===========================================================================*/

-/* External declarations.                                                    */

-/*===========================================================================*/

-

-#if !defined(__DOXYGEN__)

-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];

-#endif

-

-#ifdef __cplusplus

-extern "C" {

-#endif

-  void dmaInit(void);

-  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,

-                         uint32_t priority,

-                         stm32_dmaisr_t func,

-                         void *param);

-  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);

-#ifdef __cplusplus

-}

-#endif

-

-#endif /* _STM32_DMA_H_ */

-

-/** @} */

diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
index a7abd8e25..a6176310f 100644
--- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h
@@ -45,6 +45,15 @@
 

 /* ADC attributes.*/

 #define STM32_HAS_ADC1                      TRUE

+#define STM32_ADC_SUPPORTS_PRESCALER        FALSE

+#define STM32_ADC_SUPPORTS_OVERSAMPLING     FALSE

+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI     TRUE

+#define STM32_ADC1_HANDLER                  Vector70

+#define STM32_ADC1_NUMBER                   12

+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(1, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_ADC1_DMA_CHN                  0x00000000

+

 #define STM32_HAS_ADC2                      FALSE

 #define STM32_HAS_ADC3                      FALSE

 #define STM32_HAS_ADC4                      FALSE

@@ -63,9 +72,15 @@
 

 /* DMA attributes.*/

 #define STM32_ADVANCED_DMA                  FALSE

-#define STM32_HAS_DMA1                      TRUE

-#define STM32_HAS_DMA2                      FALSE

-#define STM32_DMA_STREAMS                   5

+#define STM32_DMA1_NUM_CHANNELS             5

+#define STM32_DMA1_CH1_HANDLER              Vector64

+#define STM32_DMA1_CH23_HANDLER             Vector68

+#define STM32_DMA1_CH4567_HANDLER           Vector6C

+#define STM32_DMA1_CH1_NUMBER               9

+#define STM32_DMA1_CH23_NUMBER              10

+#define STM32_DMA1_CH4567_NUMBER            11

+

+#define STM32_DMA2_NUM_CHANNELS             0

 

 /* ETH attributes.*/

 #define STM32_HAS_ETH                       FALSE

@@ -215,6 +230,15 @@
 

 /* ADC attributes.*/

 #define STM32_HAS_ADC1                      TRUE

+#define STM32_ADC_SUPPORTS_PRESCALER        FALSE

+#define STM32_ADC_SUPPORTS_OVERSAMPLING     FALSE

+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI     TRUE

+#define STM32_ADC1_HANDLER                  Vector70

+#define STM32_ADC1_NUMBER                   12

+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(1, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_ADC1_DMA_CHN                  0x00000000

+

 #define STM32_HAS_ADC2                      FALSE

 #define STM32_HAS_ADC3                      FALSE

 #define STM32_HAS_ADC4                      FALSE

@@ -403,6 +427,15 @@
 

 /* ADC attributes.*/

 #define STM32_HAS_ADC1                      TRUE

+#define STM32_ADC_SUPPORTS_PRESCALER        FALSE

+#define STM32_ADC_SUPPORTS_OVERSAMPLING     FALSE

+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI     TRUE

+#define STM32_ADC1_HANDLER                  Vector70

+#define STM32_ADC1_NUMBER                   12

+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(1, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_ADC1_DMA_CHN                  0x00000000

+

 #define STM32_HAS_ADC2                      FALSE

 #define STM32_HAS_ADC3                      FALSE

 #define STM32_HAS_ADC4                      FALSE

@@ -563,6 +596,15 @@
 

 /* ADC attributes.*/

 #define STM32_HAS_ADC1                      TRUE

+#define STM32_ADC_SUPPORTS_PRESCALER        FALSE

+#define STM32_ADC_SUPPORTS_OVERSAMPLING     FALSE

+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI     TRUE

+#define STM32_ADC1_HANDLER                  Vector70

+#define STM32_ADC1_NUMBER                   12

+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(1, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_ADC1_DMA_CHN                  0x00000000

+

 #define STM32_HAS_ADC2                      FALSE

 #define STM32_HAS_ADC3                      FALSE

 #define STM32_HAS_ADC4                      FALSE

@@ -721,6 +763,15 @@
 

 /* ADC attributes.*/

 #define STM32_HAS_ADC1                      TRUE

+#define STM32_ADC_SUPPORTS_PRESCALER        FALSE

+#define STM32_ADC_SUPPORTS_OVERSAMPLING     FALSE

+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI     TRUE

+#define STM32_ADC1_HANDLER                  Vector70

+#define STM32_ADC1_NUMBER                   12

+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(1, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_ADC1_DMA_CHN                  0x00000000

+

 #define STM32_HAS_ADC2                      FALSE

 #define STM32_HAS_ADC3                      FALSE

 #define STM32_HAS_ADC4                      FALSE

@@ -877,6 +928,15 @@
 

 /* ADC attributes.*/

 #define STM32_HAS_ADC1                      TRUE

+#define STM32_ADC_SUPPORTS_PRESCALER        FALSE

+#define STM32_ADC_SUPPORTS_OVERSAMPLING     FALSE

+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI     FALSE

+#define STM32_ADC1_HANDLER                  Vector70

+#define STM32_ADC1_NUMBER                   12

+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(1, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_ADC1_DMA_CHN                  0x00000000

+

 #define STM32_HAS_ADC2                      FALSE

 #define STM32_HAS_ADC3                      FALSE

 #define STM32_HAS_ADC4                      FALSE

@@ -1044,6 +1104,15 @@
 

 /* ADC attributes.*/

 #define STM32_HAS_ADC1                      TRUE

+#define STM32_ADC_SUPPORTS_PRESCALER        FALSE

+#define STM32_ADC_SUPPORTS_OVERSAMPLING     FALSE

+#define STM32_ADC1_IRQ_SHARED_WITH_EXTI     TRUE

+#define STM32_ADC1_HANDLER                  Vector70

+#define STM32_ADC1_NUMBER                   12

+#define STM32_ADC1_DMA_MSK                  (STM32_DMA_STREAM_ID_MSK(1, 1) |\

+                                             STM32_DMA_STREAM_ID_MSK(1, 2))

+#define STM32_ADC1_DMA_CHN                  0x00000000

+

 #define STM32_HAS_ADC2                      FALSE

 #define STM32_HAS_ADC3                      FALSE

 #define STM32_HAS_ADC4                      FALSE